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US 2015/0311158 A1Published application
Method of forming a high density dielectric etch-stop layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJoung-Wei Liou, Han-Ti Hsiaw, Keng-Chu Lin
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Abstract
Some embodiments of the present disclosure relate to an integrated circuit device. The integrated circuit device includes a semiconductor substrate, and an inter-level dielectric layer arranged over the semiconductor substrate. An etch-stop layer is arranged over the inter-level dielectric layer. The etch-stop layer comprises silicon oxide, silicon nitride, or silicon oxynitride, and has a density greater than or equal to 2.15 g/cm3.
Claims20
An integrated circuit device, comprising:
- a semiconductor substrate;
- an inter-level dielectric layer arranged over the semiconductor substrate;
- and
- an etch-stop layer arranged over the inter-level dielectric layer, the etch-stop layer comprising silicon oxide, silicon nitride, or silicon oxynitride, and having a density greater than or equal to 2.15 g/cm3.
1 more element
An integrated circuit device, comprising:
- a semiconductor substrate;
- an inter-level dielectric layer over the semiconductor substrate;
- and
- a compressed dielectric layer over the inter-level dielectric layer, the compressed dielectric layer being under sufficient compressive stress to significantly increase its density and resistance to plasma etching.
1 more element
An integrated circuit device comprising:
- a semiconductor substrate;
- an inter-level dielectric layer disposed over the semiconductor substrate;
- an etch-stop layer comprising silicon oxide, silicon nitride, or silicon oxynitride disposed directly over the inter-level dielectric layer, the etch-stop layer having a density greater than or equal to 2.15 g/cm3;
- a protective layer disposed directly over an upper surface of the etch-stop layer;
- a low-k dielectric layer disposed directly over an upper surface of the protective layer;
- a metal plug extending downwardly through the inter-level dielectric layer and the etch-stop layer to a source/drain region within the semiconductor substrate;
- and
- a copper via extending downwardly through the low-k dielectric layer and to connect with the metal plug.
5 more elements
Dependencies are inferred from the claim text.