US 2015/0311112 A1Published application

Patterning Method For Low-K Inter-Metal Dielectrics And Associated Semiconductor Device

AssigneeSanDisk Technologies LLC

InventorNoritaka Fukuo

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Abstract

Semiconductor fabrication techniques and associated semiconductor devices are provided in which conductive lines are separated by a low dielectric constant (low-k) material such as low-k film portions or air. An insulation layer such as SiO2 is etched to form raised structures. The structures are slimmed and a low-k material or sacrificial material is deposited. A further etching removes the material except for portions on sidewalls of the slimmed structures. A metal barrier layer and seed layer are then deposited, followed by a metal filler such as copper. Chemical mechanical polishing (CMP) removes portions of the metal above the raised structures, leaving only portions of the metal between the raised structures as spaced apart conductive lines. The sacrificial material can be removed by a thermal process, leaving air gaps. The raised structures provide strength while the air gap or other low-k material reduces capacitance.

Claims20

Dependent claims

A method for fabricating a semiconductor structure, comprising:

patterning an insulation layer carried on a substrate, the patterning forms at least first and second ridges in the insulation layer which are spaced-apart from one another;
slimming the first and second ridges to form first and second slimmed ridges, respectively;
depositing an inter-metal material, the inter-metal material conforming to a shape of the first and second slimmed ridges;
performing an etching operation, the etching operation etches through portions of the inter-metal material, resulting in a first raised structure comprising portions of the inter-metal material on opposing sides of the first slimmed ridge and a second raised structure comprising portions of the inter-metal material on opposing sides of the second slimmed ridge;
providing a barrier metal layer, the barrier metal layer conforming to a shape of the first and second raised structures;
providing a metal filler over the barrier metal layer, the metal filler extending above and between the first and second raised structures;
and
performing a planarizing operation, the planarizing operation results in planarizing of the first and second raised structures to form first and second planarized structures, respectively, and planarizing of the metal filler to form a remaining portion of the metal filler as an elongated conductive line which extends between, but not above, the first and second planarized structures.

5 more elements

A semiconductor structure, comprising:

a first insulative ridge comprising a peak, a first concave sidewall extending from the peak of the first insulative ridge down to a base of the first insulative ridge, and a second concave sidewall extending from the peak of the first insulative ridge down to the base of the first insulative ridge, the first concave sidewall faces away from the second concave sidewall;
a first elongated metal line on one side of the first insulative ridge;
a second elongated metal line on another side of the first insulative ridge, and spaced apart from the first elongated metal line;
a first portion of a barrier metal between the first elongated metal line and the first concave sidewall;
a second portion of the barrier metal between the second elongated metal line and the second concave sidewall;
a low-k dielectric material between the first concave sidewall and the first portion of the barrier metal;
and
a low-k dielectric material between the second concave sidewall and the second portion of the barrier metal.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/260,867Filed 24 Apr 2014
Published: 29 Oct 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10W 20/075
Of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers: of multilayered…
H10W 20/033
Of conductive barrier, adhesion or liner layers: in openings in dielectrics
H10W 20/042
Of conductive barrier, adhesion or liner layers: the barrier, adhesion or liner layers being seed or nucleation layers
H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches