Tungsten salicide gate source for vertical nand string to control on current and cell pillar fabrication
AssigneeIntel Corporation
InventorsFatma Arzum Simsek-Ege, Krishna K. Parat
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Abstract
A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer in place of a conventionally used aluminum oxide to form channel pillars having a high aspect ratio. Use of the tungsten salicide is useful for eliminating an undesired etch-stop recess and an undesired floating gate that is formed when an Al oxide etch-stop layer is conventionally used.
Claims13
1-20. (canceled)
A memory device, comprising:
- a channel comprising a first end and a second end, the first end of the channel being coupled to a bit line and the second end of the channel being coupled to a source;
- a select gate formed at the second end of the channel to selectively control conduction between the bit line and the channel, the select gate comprising a layer of tungsten salicide;
- at least one non-volatile memory cell formed along a length of the channel between the select gate and the first end of the channel;
- and at least one word line coupled to the at least one non-volatile memory cell;
- wherein a distance between the select gate and the at least one word line measures less than 50 nanometers.
The memory device according to claim 1, wherein the memory device comprises part of an array of memory devices.
The memory device according to claim 1, wherein the select gate comprises a layer of tungsten salicide formed between two polysilicon layers.
The memory device according to claim 1, wherein a distance between the select gate and the at least one word line measures approximately 30 nanometers.
A memory device, comprising:
- a channel comprising a first end and a second end, the first end of the channel being coupled to a bit line and the second end of the channel being coupled to a source;
- a select gate formed at the second end of the channel to selectively control conduction between the bit line and the channel, the select gate comprising a layer of tungsten salicide;
- the select gate being adjacent to a layer of polysilicon;
- at least one non-volatile memory cell formed along a length of the channel between the select gate and the first end of the channel;
- and at least one word line coupled to the at least one non-volatile memory cell;
- wherein a distance between the select gate and the at least one word line measures less than 50 nanometers.
Dependencies are inferred from the claim text.