Method for Improving E-Beam Lithography Gate Metal Profile for Enhanced Field Control

A method for forming a gallium nitride semiconductor device, comprising:

• providing a semiconductor substrate comprising a gallium nitride surface layer,
• covering the semiconductor substrate with a plurality of dielectric layers;
• providing a patterned multi-layer resist stack overlying the plurality of dielectric layers with a mask opening located above the semiconductor substrate, the mask opening comprising a narrow bottom opening portion which exposes a top portion of the plurality of dielectric layers, a wider middle opening portion aligned over the narrow bottom opening portion, and a top opening portion that is aligned over and narrower than the middle opening portion;
• etching through a top dielectric layer from the plurality of dielectric layers exposed by the narrow bottom opening portion of the patterned multi-layer resist stack to form a first opening in the top dielectric layer having a first width which exposes a middle dielectric layer from the plurality of dielectric layers;
• etching through the middle dielectric layer from the plurality of dielectric layers exposed by the first opening to form a second opening in the middle dielectric layer having the first width which exposes a bottom dielectric layer from the plurality of dielectric layers while simultaneously widening the narrow bottom opening portion of the patterned multi-layer resist stack to expose an additional portion of the top dielectric layer;
• etching through the bottom dielectric layer from the plurality of dielectric layers exposed by the second opening to form a third opening in the bottom dielectric layer having the first width which exposes a first portion of the gallium nitride surface layer while simultaneously widening the first opening in the top dielectric layer to form a wider first opening;
• forming a stepped field plate structure in contact with at least part of the exposed first portion of the gallium nitride surface layer by filling the wider first opening, second opening, and third opening with one or more conductive layers, where the stepped field plate structure comprises a gate length contact base having a gate length and one or more gate ledges, and gate electrode sidewall extensions formed to be vertically spaced apart from the plurality of dielectric layers.

A semiconductor device, comprising:

• a substrate;
• a multi-layer dielectric stack covering the substrate with a stepped electrode opening defined by a lower dielectric layer opening which exposes the substrate and a wider upper dielectric layer opening that is aligned with the lower dielectric layer opening;
• and
• a conductive electrode located at least in part in the stepped electrode opening to be in contact with the substrate, where the conductive electrode comprises a lower contact base portion having vertical sidewalls formed in the lower dielectric layer opening, a middle portion having vertical sidewalls formed in the wider upper dielectric layer opening, and upper electrode sidewall extensions formed to be vertically spaced above the multi-layer dielectric stack by a first vertical gap distance.