Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices

A method, comprising:

• forming a sacrificial gate structure above a surface of a semiconductor substrate, said sacrificial gate structure comprising a sacrificial gate insulation layer, a lower sacrificial gate electrode positioned above said sacrificial gate insulation layer and an upper sacrificial gate electrode positioned above said lower sacrificial gate electrode, wherein said upper sacrificial gate electrode and said lower sacrificial gate electrode are made of materials that may be selectively etched relative to one another;
• forming a sidewall spacer adjacent opposite sides of at least said lower sacrificial gate electrode and said upper sacrificial gate electrode;
• forming a layer of insulating material adjacent said sidewall spacers;
• performing at least one first etching process through a patterned mask layer so as to thereby define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that each expose a portion of a surface of said lower sacrificial gate electrode;
• performing at least one second etching process through said patterned upper sacrificial gate electrode to remove said lower sacrificial gate electrode and said sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under said patterned upper sacrificial gate electrode;
• and
• performing at least one process operation to form a first portion of a replacement gate structure positioned in at least the first portion of said replacement gate cavity under said patterned upper sacrificial gate electrode.

A transistor device, comprising:

• a semiconductor substrate;
• a gate structure positioned above a surface of said semiconductor substrate, said gate structure comprising:
• a high-k gate insulation layer positioned above said surface of said substrate;
• at least one work-function adjusting layer of material positioned above said high-k gate insulation layer, said at least one work-function adjusting layer of material having an upper surface with a stepped profile when viewed in cross-section taken in a gate-width direction of said transistor device;
• and
• a layer of conductive material positioned on said stepped upper surface of said at least one work-function adjusting layer of material;
• a sidewall spacer positioned adjacent opposite sides of at least a portion of said gate structure;
• and
• a gate cap layer positioned above said layer of conductive material.