Configurable Test Address And Data Generation For Multimode Memory Built-In Self-Testing

An integrated circuit comprising built-in self-test (BIST) circuitry for multiport memory, the BIST circuitry comprising:

• a configurable address generator that can be configured to generate first and second logical memory addresses corresponding to physically neighboring first and second memory cells of the multiport memory for a selected memory mode of a plurality of available memory modes having different column-multiplexing schemes;
• and
• a configurable data generator that can be configured to generate first and second sets of data for the selected memory mode, such that:
• the first set of data is written into and read from the multiport memory via a first memory port using the first logical memory address;
• and
• the second set of data is written into and read from the multiport memory via a second memory port using the second logical memory address.

An integrated circuit comprising built-in self-test (BIST) circuitry for multiport memory, the BIST circuitry comprising:

• a configurable address generator that can be configured to generate first and second logical memory addresses corresponding to first and second memory cells of the multiport memory for a selected memory mode of a plurality of available memory modes having different column-multiplexing schemes;
• and
• a configurable data generator that can be configured to generate first and second sets of data for the selected memory mode, such that:
• the first set of data is written into and read from the multiport memory via a first memory port using the first logical memory address;
• and
• the second set of data is written into and read from the multiport memory via a second memory port using the second logical memory address.