US 2015/0310929 A1Published application

Semiconductor device, display module, and electronic device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorAtsushi UMEZAKI

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Abstract

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to third transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

Claims22

Dependent claims

A semiconductor device comprising a shift register,

wherein the shift register includes first to third flipflops,
wherein the first flipflop has a function of outputting a first signal to a first wiring,
wherein the second flipflop has a function of outputting a second signal to a second wiring,
wherein the third flipflop has a function of outputting a third signal to a third wiring,
wherein the first signal has a value synchronized with a first clock signal,
wherein the second signal has a value synchronized with a second clock signal,
wherein the third signal has a value synchronized with a third clock signal,
wherein the second flipflop includes first to third transistors,
wherein one of a source and a drain of the first transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor,
wherein a gate of the second transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the third transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein a gate of the third transistor is electrically connected to a sixth wiring,
wherein the fourth wiring has a function of transmitting the second clock signal,
wherein the fifth wiring has a function of transmitting the first clock signal, and
wherein the sixth wiring has a function of transmitting the third clock signal.

16 more elements

A semiconductor device comprising a shift register,

wherein the shift register includes first to third flipflops,
wherein the first flipflop has a function of outputting a first signal to a first wiring,
wherein the second flipflop has a function of outputting a second signal to a second wiring,
wherein the third flipflop has a function of outputting a third signal to a third wiring,
wherein the first signal has a value synchronized with a first clock signal,
wherein the second signal has a value synchronized with a second clock signal,
wherein the third signal has a value synchronized with a third clock signal,
wherein the second flipflop includes first to third transistors,
wherein one of a source and a drain of the first transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to a fifth wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor,
wherein a gate of the second transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a sixth wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor,
wherein a gate of the third transistor is electrically connected to the third wiring,
wherein the fourth wiring has a function of transmitting the second clock signal,
wherein the fifth wiring has a function of transmitting the first clock signal, and
wherein the sixth wiring has a function of transmitting the third clock signal.

16 more elements

A semiconductor device comprising a shift register,

wherein the shift register includes first to fifth flipflops,
wherein the first flipflop has a function of outputting a first signal to a first wiring,
wherein the second flipflop has a function of outputting a second signal to a second wiring,
wherein the third flipflop has a function of outputting a third signal to a third wiring,
wherein the fourth flipflop has a function of outputting a fourth signal to a fourth wiring,
wherein the fifth flipflop has a function of outputting a fifth signal to a fifth wiring,
wherein the first signal has a value synchronized with a first clock signal,
wherein the second signal has a value synchronized with a second clock signal,
wherein the third signal has a value synchronized with a third clock signal,
wherein the fourth signal has a value synchronized with a fourth clock signal,
wherein the fifth signal has a value synchronized with the first clock signal,
wherein the third flipflop includes first to fifth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to a sixth wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the third transistor is electrically connected to the fourth wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor,
wherein at least one of a gate and one of a source and a drain of the fourth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the second transistor,
wherein at least one of a gate and one of a source and a drain of the fifth transistor is electrically connected to the fifth wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the third transistor, and
wherein the sixth wiring has a function of transmitting the third clock signal.

20 more elements

A semiconductor device comprising a shift register,

wherein the shift register includes first to third flipflops,
wherein the first flipflop has a function of outputting a first signal to a first wiring,
wherein the second flipflop has a function of outputting a second signal to a second wiring,
wherein the third flipflop has a function of outputting a third signal to a third wiring,
wherein the first signal has a value synchronized with a first clock signal,
wherein the second signal has a value synchronized with a second clock signal,
wherein the third signal has a value synchronized with a third clock signal,
wherein the second flipflop includes first to fifth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the third transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor,
wherein at least one of a gate and one of a source and a drain of the fourth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the second transistor,
wherein at least one of a gate and one of a source and a drain of the fifth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the third transistor, and
wherein the fourth wiring has a function of transmitting the second clock signal.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/680,520Filed 7 Apr 2015
Priority: JP 2014-09031424 Apr 2014
Published: 29 Oct 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G09G 3/3674
Control of matrices with row and column drivers: details of drivers for scan electrodes
G09G 3/20
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes: for presentation of an…
G09G 3/3688
Details of drivers for data electrodes: suitable for active matrices only
G11C 19/28
Digital stores in which the information is moved stepwise, e.g. shift registers: using semiconductor elements