Low-pin-count non-volatile memory interface with soft programming capability

An electronics system, comprising:

• a processor;
• and
• at least one low-pin-count nonvolatile memory (NVM) operatively connected to the processor, the NVM includes at least a plurality of NVM cells for providing data storage, at least one of the NVM cells comprising:
• a NVM element coupled to a first supply voltage line;
• a selector coupled to the NVM element and a second supply voltage line having a select signal;
• a first signal input for receiving a first signal;
• a second signal input for receiving a second signal;
• and
• wherein a transaction starts based on a voltage level of the first signal during a transition of the second signal,
• wherein the transaction includes at least one mode cycle and a plurality of data cycles to specify operation modes and programming, erasing, or reading the NVM cells, respectively, once the transaction starts, and
• wherein the NVM cells are selected sequentially for program, erase, or read when the voltage of the first signal is coupled to the first or second supply voltage level during the data cycles.

A One-Time Programmable (OTP) memory integrated in an integrated circuit comprises a plurality of OTP cells, each of the plurality of OTP cells comprising:

• an OTP element coupled to a first supply voltage line;
• a selector coupled to the OTP element and a second supply voltage line having a select signal;
• a first signal input for receiving a first signal;
• and
• a second signal input for receiving a second signal,
• wherein a transaction starts based on conditions on the first signal input and the second signal input, and
• wherein the transaction includes at least one mode cycle and a plurality of data cycles to specify operation modes and programming, erasing, or reading the OTP elements, respectively.