Eprom cell array, method of operating the same, and memory device including the same
AssigneeSK hynix Inc.
InventorYong Seop LEE
Life of this patent
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Abstract
An EPROM cell array includes a cell array including multiple unit cells, each of which includes a MOSFET having a floating gate, and which are disposed in an array with a plurality of rows and a plurality of columns; multiple first selection lines each coupled with drains of unit cells, which are disposed on the same row among the multiple unit cells; and multiple second selection lines each coupled with sources of unit cells, which are disposed on the same column among the unit cells, wherein a selected unit cell to be programmed or read is selected by one of the multiple first selection lines, and one of the multiple second selection lines
Claims20
An EPROM cell array comprising:
- a cell array including multiple unit cells, each of which includes a MOSFET having a floating gate, and which are disposed in an array with a plurality of rows and a plurality of columns;
- multiple first selection lines each coupled with drains of unit cells, which are disposed on the same row among the multiple unit cells;
- and
- multiple second selection lines each coupled with sources of unit cells, which are disposed on the same column among the unit cells,
- wherein a selected unit cell to be programmed or read is selected by one of the multiple first selection lines, and one of the multiple second selection lines.
A method for operating an EPROM cell array including a cell array having multiple unit cells each of which includes a MOSFET having a floating gate, and which are disposed in an array with a plurality of rows and a plurality of columns, multiple first selection lines each coupled with drains of unit cells disposed on the same row among the unit cells, and multiple second selection lines each coupled with sources of unit cells disposed on the same column among the unit cells, the method comprising:
- selecting one of the multiple unit cells by applying 0V to one of the multiple first selection lines, by applying an operation voltage to one of the multiple second selection lines, and by floating the remaining multiple first and second selection lines;
- and
- performing an operation on the selected unit cell.
A memory device comprising:
- an EPROM cell array including a cell array having multiple unit cells, each of which includes a MO FET having a floating gate, and which are disposed in an array with a plurality of rows and a plurality of columns, multiple first selection lines each coupled with drains of unit cells disposed on the same row among the unit cells, and multiple second selection lines each coupled with sources of unit cells disposed on the same column among the unit cells;
- a switching block suitable for selectively applying 0V to one or more of the multiple first selection lines;
- a first demultiplexer suitable for selectively enabling the switching block;
- a second demultiplexer suitable for selecting one or more of the multiple second selection lines;
- and
- one or more switching elements suitable for transferring the program voltage or the read voltage to the second demultiplexer.
A memory device comprising:
- an EPROM cell array including a cell array having multiple unit cells, each of which includes a MOSFET having a floating gate, and which are disposed in an array with a plurality of rows and a plurality of columns, multiple first selection lines each coupled with drains of unit cells disposed on the same row among the unit cells, and multiple second selection lines each coupled with sources of unit cells disposed on the same column among the unit cells;
- a switching block suitable for selectively applying 0V to one or more of the multiple first selection lines;
- a first demultiplexer suitable for selectively enabling the switching block;
- multiple sense amplifiers coupled to the multiple second selection lines, respectively;
- and
- multiple switching elements coupled between the multiple second selection lines and the multiple sense amplifiers, respectively, and suitable for selectively transferring the program voltage or the read voltage to the multiple second selection lines.
A cell array comprising:
- multiple unit cells, each of which includes one or more MOSFETs;
- multiple row selection lines, each of which is coupled to the unit cells of a row in the cell array;
- and
- multiple column selection lines, each of which is coupled to the unit cells of a column in the cell array,
- wherein a selected unit cell for program or read operations is selected in the cell array by one of the multiple row selection lines, to which a reference voltage is applied, and one of the multiple column selection lines, to which an operation voltage is applied.
Dependencies are inferred from the claim text.