Nonvolatile memory system
AssigneeSamsung Electronics Co., Ltd.
InventorHYOTAEK LEEM
Life of this patent
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Abstract
A nonvolatile memory system is provided. The memory system includes a nonvolatile memory device and a memory controller. The memory controller transmits first to fourth control signals to the nonvolatile memory device, sends a command, an address, and input data via a data bus, and receives output data via the data bus. The nonvolatile memory device receives the first to fourth control signals, and recognizes signals received via the data bus at a rising edge or a falling edge of the fourth control signal, as one of the command, the address, and the input data in response to the first to third control signals, and transfers the output data to the memory controller via the data bus based on the fourth control signal.
Claims20
A memory controller comprising;
- a first control pin and a second control pin configured to indicate one of an address state, a command state, or a data state of the memory controller;
- a plurality of data pins configured to transmit and receive a command signal, an address signal, and a data signal from/to a memory device;
- and
- a third control pin configured to transmit a data strobe signal to the memory device to indicate a timing to latch the address signal, the command signal, and the data signal.
A memory device comprising;
- a first control pin and a second control pin configured to indicate one of an address state, a command state, or a data state of the memory device;
- a plurality of data pins configured to transmit and receive a command signal, an address signal, and a data signal from/to the memory device;
- and
- a third control pin configured to transmit a data strobe signal to a memory controller to indicate a timing to latch the address signal, the command signal, and the data signal synchronized with the data strobe signal.
A memory system comprising;
- a memory controller;
- and
- a memory device connected to the memory controller through a control bus and a data bus,
- wherein the control bus transmits first and second control signals, and a data strobe signal from the memory controller to the memory device,
- wherein the first and second control signals indicate one of an address state, a command state, or a data state of the memory system, and the data strobe signal indicates a timing to latch a data signal,
- wherein the data bus transmits a command signal, an address signal, and the data signal synchronized with the data strobe signal between the memory controller and the memory device.
Dependencies are inferred from the claim text.