Optimization of circuit layout area of a memory device
AssigneeBroadcom Corporation
InventorScott Yu-Fan CHU
Life of this patent
Estimating the term…
Abstract
A memory cell including a storage cell, a write port cell, and a read port cell is discussed. The storage cell is configured to store a logic value. The write port cell is configured to write the logic value. The read port cell is configured to read the stored logic value and includes a plurality of read ports. At least a first port of the plurality of read ports includes a first and a second active diffusion region that are each configured to be used for implementation of a second p-channel transistor. At least a second read port of the plurality of read ports includes a third and fourth active diffusion regions that are each configured to be used for implementation of a second n-channel transistor.
Claims20
A memory cell, comprising:
- a storage cell configured to store a logic value;
- a write port cell coupled to the storage cell configured to write the logic value;
- and
- a read port cell coupled to the storage cell configured to read the stored logic value, the read port cell comprising a plurality of read ports,
- wherein a first read port of the plurality of read ports includes a first p-channel transistor and a second p-channel transistor, and
- wherein a second read port of the plurality of read ports includes a first n-channel transistor and a second n-channel transistor.
A memory cell, comprising:
- a storage cell configured to store a logic value;
- a write port cell, coupled to the storage cell, configured to write the logic value;
- and
- a read port cell, coupled to the storage cell, configured to read the stored logic value, the read port cell comprising a plurality of read ports,
- wherein a first read port of the plurality of read ports includes a first active diffusion region and a second active diffusion region, the first active diffusion region being configured to be used for implementation of a first p-channel transistor and the second active diffusion region being configured to be used for implementation of a second p-channel transistor, and
- wherein a second read port of the plurality of read ports includes a third active diffusion region and a fourth active diffusion region, the third active diffusion region being configured to be used for implementation of a first n-channel transistor and the second active diffusion region being configured to be used for implementation of a second n-channel transistor.
A semiconductor device, comprising:
- a storage cell configured to store a logic value;
- a write port cell configured to write the logic value;
- and
- a read port cell configured to read the stored logic value, the read port cell comprising a first read port and a second read port,
- wherein the first read port includes a first active diffusion region and a second active diffusion region, the first active diffusion region being configured to be used for implementation of a first p-channel transistor and the second active diffusion region being configured to be used for implementation of a second p-channel transistor, and
- wherein the second read port includes a third active diffusion region and a fourth active diffusion region, the third active diffusion region being configured to be used for implementation of a first n-channel transistor and the second active diffusion region being configured to be used for implementation of a second n-channel transistor.
Dependencies are inferred from the claim text.