Semiconductor Memory Device Including Power Supply Line
AssigneeMicron Technology, Inc.
InventorMinoru YAMAGAMI
Life of this patent
Estimating the term…
Abstract
A semiconductor apparatus disclosed in this disclosure includes a first channel formed in a first area and including a first power supply pad, a first clock pad, a first command address pad, a first data input/output pad and a first memory cell array; a second channel formed in a second area and including a second power supply pad, a second clock pad, a second command address pad, a second data input/output pad and a second memory cell array, the first and second channels being independently controllable from each other; and mesh structure lines straddling the first area and second area and connected to the first and second power supply pads.
Claims16
A semiconductor apparatus comprising:
- a plurality of first pads including a first power supply pad and a first data input/output pad, the plurality of first pads aligned to a first line elongated in a first direction;
- a plurality of second pads including a second power supply pad and a second data input/output pad, the plurality of second pads aligned to a second line elongated in the first direction;
- first and second memory cell arrays arranged between the plurality of first pads and the plurality of second pads in a second direction crossing the first direction;
- a first main amplifier arranged between the first memory cell array and the plurality of first pads;
- a second main amplifier arranged between the second memory cell array and the plurality of second pads;
- a first data input/output circuit coupled between the first data input/output pad and the first main amplifier;
- a second data input/output circuit coupled between the second data input/output pad and the second main amplifier;
- a first signal line coupled between the first main amplifier and the first data input/output circuit;
- a second signal line coupled between the second main amplifier and the second data input/output circuit;
- and
- a first power supply line arranged between the first and second main amplifiers and coupled to the first and second power supply pads.
A semiconductor apparatus including a first area and a second area, comprising:
- a first channel formed in the first area and including a first power supply pad, a first clock pad, a first command address pad, a first data input/output pad and a first memory cell array;
- a second channel formed in the second area and including a second power supply pad, a second clock pad, a second command address pad, a second data input/output pad and a second memory cell array, the first and second channels being independently controllable from each other;
- and
- mesh structure lines straddling the first area and second area and connected to the first and second power supply pads.
Dependencies are inferred from the claim text.