US 2015/0310904 A1 · SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY

Abstract

In a memory having a first memory cell array, a second memory cell array, an address is received on an address port. Based on the address, an internal address is transmitted, and it is latched and held for a first interval as a first array address. The first memory cell array is accessed over the first interval, based on the first array address. Another address is received at the address port, during the first interval, and another internal address is transmitted, and latched and held for a second interval that overlaps the first interval, as a second array address. The second memory cell array is accessed during the second interval, based on the second array address.

Claims20

Dependent claims

A method for read/write of a memory having a first memory cell array, a second memory cell array, a data in port, a data out port, and a command/address port, comprising:

receiving a clock, wherein the clock includes a first edge, a second edge and a third edge, spaced apart by a clock period
receiving, in association with the first edge, a command at the command/address port to access a memory cell in the first memory cell array;
in response to the command to access a memory cell in the first memory cell array, accessing the memory cell over a first interval, wherein the first interval begins prior to the second edge and extends past the second edge;
receiving, in association with the second edge, a command at the command/address port to access a memory cell in the second memory cell array;
and
in response to the command to access a memory cell in the second memory cell array, accessing said memory cell over a second interval, wherein the second interval overlaps the first interval.

3 more elements

A method for read/write of a memory having a first memory cell array, a second memory cell array, a data in port, a data out port, and an address port, comprising

receiving an address on the address port and, based on the address, transmitting an internal address;
receiving the internal address by a first address latch and holding the internal address on the first address latch as a first array address, over a first interval;
accessing the first memory cell array, during the first interval, based on the first array address;
receiving another address on the address port and, based on the another address, transmitting another internal address;
receiving the another internal address by a second address latch and holding the another internal address on the second address latch as a second array address, over a second interval, wherein the second interval overlaps the first interval;
and
accessing the second memory cell array, during the second interval, based on the second array address.

4 more elements

A resistive memory cell device, comprising

an address bus;
a control block configured to receive an externally generated address, a command and a clock and, in response, transmit an internal address on the address bus, and generate a first sub-bank address latch control and a second sub-bank address latch control;
a first sub-bank having a first array of resistive memory cells and a first sub-bank latching access circuitry that is configured to access a resistive memory cell in the first array of resistive memory cells according to a value of the internal address and maintain the access over a first interval based on the first sub-bank address latch control;
and
a second sub-bank having a second array of resistive memory cells and a second sub-bank latching access circuitry that is configured to access a resistive memory cell in the second array of resistive memory cells according to an updated value of the internal address and maintain said access over a second interval based on the second sub-bank address latch control,
wherein the control block is configured to generate the first latch control and the second latch control so that the second interval overlaps the first interval.

3 more elements

Dependencies are inferred from the claim text.

System and method of concurrent read/write magneto-resistive memory

Life of this patent

System and method of concurrent read/write magneto-resistive memory

Life of this patent

Abstract

Claims20