Static Power Reduction in Caches Using Deterministic Naps
OwnerOluleye Olorode, Mehrdad Nouraniinventors
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Abstract
The dNap architecture is able to accurately transition cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.
Claims7
A cache memory system, comprising:
- a cache memory operable to store data in a plurality of locations defined by a plurality of addresses and divided into a plurality of cache ways;
- a memory nap controller operable to track in-flight cache accesses and further operable to control the desired power state of a plurality of data RAM lines;
- a processing block operable to group a plurality of contiguous cache lines into a single power group.
Dependencies are inferred from the claim text.