Semiconductor device and data processing system

A semiconductor device comprising:

• a memory control circuit for controlling a DDR type SDRAM;
• and
• a plurality of access-requesting circuits each operable to make a request for an access to the SDRAM to the memory control circuit,
• wherein the memory control circuit issues an access command in response to an access request from one said access-requesting circuit, a refresh command to make a request for a refresh operation for reproducing stored information of the SDRAM based on a set refresh cycle, and a calibration command to make a request for a calibrating operation for correcting a termination resistance of the SDRAM based on a set calibration cycle, and
• wherein the memory control circuit includes a first register for specifying a period during which the issue of the calibration command is restricted after issuance of the refresh command, and a second register for specifying a period during which the issue of the refresh command is restricted after issuance of the calibration command.

A microcomputer comprising:

• a CPU;
• a bus connected to the CPU;
• a DDR type SDRAM connected to the bus;
• and
• a memory control circuit for controlling the SDRAM,
• wherein the memory control circuit issues an access command in response to an access request from the CPU, a refresh command to make a request for a refresh operation for reproducing stored information of the SDRAM based on a set refresh cycle, and a calibration command to make a request for a calibrating operation for correcting a termination resistance of the SDRAM based on a set calibration cycle, and
• wherein the memory control circuit includes a first register for specifying a period during which the issue of the calibration command is restricted after the issue of the refresh command, and a second register for specifying a period during which the issue of the refresh command is restricted after the issue of the calibration command.