Differential amplifier circuit and display drive circuit

A differential amplifier circuit comprising:

• a differential pair transistor configured to receive a differential input signal;
• a current source which is connected in series to the differential pair transistor;
• and
• an output transistor configured to drive an output terminal,
• wherein the output transistor is constituted by a first P-channel MOS transistor which is connected between a high-potential-side power supply and the output terminal and a first N-channel MOS transistor which is connected between a low-potential-side power supply and the output terminal,
• the differential pair transistor is constituted by a third P-channel MOS transistor and a third N-channel MOS transistor in which a gate terminal is configured to receive one differential input signal, and a fourth P-channel MOS transistor and a fourth N-channel MOS transistor in which a gate terminal is configured to receive one differential input signal,
• the current source is configured such that a high-potential-side constant current source that supplies a positive current from the high-potential-side power supply and a second P-channel MOS transistor are connected in parallel to each other, and that a low-potential-side constant current source that supplies a negative current from the low-potential-side power supply and a second N-channel MOS transistor are connected in parallel to each other, supplies the positive current from the high-potential-side power supply to source terminals of the third P-channel MOS transistor and the fourth P-channel MOS transistor, and supplies the negative current from the negative-potential-side power supply to source terminals of the third P-channel MOS transistor and the fourth P-channel MOS transistor, and
• the positive current which is supplied from the high-potential-side power supply is increased by controlling a gate terminal of the second P-channel MOS transistor using a signal which is input to agate terminal of the first P-channel MOS transistor, and an absolute value of the negative current which is supplied from the low-potential-side power supply is increased by controlling a gate terminal of the second N-channel MOS transistor using a signal which is input to a gate terminal of the first N-channel MOS transistor.