Gate Driver for Narrow Bezel LCD
AssigneeShenzhen China Star Optoelectronics Technology Co., Ltd.
InventorJuncheng Xiao
Life of this patent
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Abstract
The present invention proposes a gate driver which simplifies a circuit structure by effectively compounding the pull-down holding circuit and signals to achieve a design for ultra-narrow bezel gate driver. In addition, It effectively lessens voltage offset at the second node and prolongs GOA circuit operating time to prolongs lifetime of the LCD when the seventh transistor of the first pull-down holding circuit adopts equivalent diode connection. At last, it reduces RC delay to efficiently lower power-consumption to more effectively decrease LCD energy-consumption when amount of transistors and signals of the first and the second pull-down holding circuits decreases.
Claims10
A gate driver comprising:
- a plurality of cascaded connected shift register units, each shift register unit for outputting output signal pulses at an output end of each of the shift register units according to a first clock signal, a second clock signal and a driving signal pulse from a previous one shift register unit of each of the shift register units, each shift register unit comprising:
- a pull-up circuit, comprising a first transistor whose a gate coupled to a first node, a source coupled to a first clock signal and a drain coupled to the output end, for providing the output signal pulses from the output end according to the first clock signal;
- a transfer circuit, comprising a second transistor whose a gate coupled to the first node, a source coupled to a first clock signal, and a drain coupled to a driving signal end, for outputting the driving signal pulse from the driving signal end according to the first clock signal;
- a pull-up control circuit, comprising a third transistor whose a gate coupled to an output signal end of the previous one shift register unit, a source coupled to a driving signal end of the previous one shift register end, a drain coupled to the first node, for conducting the pull-up circuit according to the driving signal pulses of the previous one shift register unit;
- a boost circuit, coupled between the first node and the output end, for boosting potentials of the first node;
- a first pull-down holding circuit, coupled to the first node, the first clock signal, a first constant voltage and a second constant voltage, for maintaining the first node at low voltage level;
- a second pull-down holding circuit, coupled to the first node, a driving signal end of next two shift register unit, the first constant voltage and the second constant voltage, for pulling down potentials of the first node according to driving signals of the next two shift register unit;
- and
- a pull-down circuit, coupled to the first constant voltage, the driving signal end and a driving signal end of a next one shift register unit, for pulling-down the potential of the first node to the first constant voltage.
Dependencies are inferred from the claim text.