Dynamically reconstructable multistage parallel single instruction multiple data array processing system

A dynamically reconstructable multistage parallel single instruction multiple data array processing system, which is applied for rapid image feature extraction and feature recognition of high speed vision image on a high speed on-chip vision system, the system comprising:

• a configurable image sensor interface used to receive pixel data from an image sensor serially or in parallel and to output the pixel data in row-parallel to a subsequent dynamically reconfigurable parallel image processing element array and self organizing map neural network;
• the dynamically reconfigurable parallel image processing element array and self organizing map neural network with dynamical reconfigurability to be an M×M pixel-level parallel processing element array or an (M/4)×(M/4) self organizing map SOM neural network so as to implement image feature extraction and image feature recognition during the respective stages of the image processing, wherein M is a natural number;
• a row processor array used to assist the dynamically reconfigurable parallel image processing element array and self organizing map neural network to implement relative image processing tasks during the respective stages of image processing adapted to being parallel processed by row, to implement a rapid nonlinear processing and a global image processing, and to serially shift in data and output processing results under external control of the system;
• and
• an array controller used to, under control of a driver external to the system, read control instructions for controlling the dynamically reconfigurable parallel image processing element array and self organizing map neural network and the RP array from a variable very long instruction word single instruction multiple data VVS instruction memory internal to the system, and used to decode the control instructions along with some values of their own specific registers to be output to the dynamically reconfigurable parallel image processing element array and self organizing map neural network and the RP array as an array control signal.