Computer-implemented verification system for performing a functional verification of an integrated circuit

A computer-implemented verification system for performing at least one of a system level or a system on chip level functional verification of an integrated circuit, said computer-implemented verification system comprising:

• one or more processors;
• a memory storing instructions defined by one or more modules of said computer-implemented verification system, wherein said one or more processors are configured to execute said instructions, said one or more modules comprising:
• a scenario compiler for:
• receiving a set of verification scenario intents from a user, wherein set of verification scenario intents comprises at least one of:
• a) one or more test-application intents, b) one or more constraints, c) one or more device-programming intents and d) one or more scenario-control intents;
• and
• generating one or more open verification methodology (OVM) and/or universal verification methodology (UVM) compliant test bench sequences and one or more scenario software implementations based on said set of verification scenario intents;
• a verification component configured to interact with said integrated circuit using said generated one or more OVM and/or UVM compliant test bench sequences;
• and
• a software library component for enabling execution of said scenario software implementations on at least one processing unit core of said integrated circuit.