Method for Integrated Circuit Manufacturing

A method comprising:

• receiving a design layout of an integrated circuit (IC), wherein the design layout includes a plurality of IC regions, and each of the IC regions includes an identical initial IC design pattern;
• performing a location effect analysis to the IC design layout thereby dividing the IC regions into a plurality of groups, wherein each group includes at least one of the IC regions and all IC regions in each group are to have substantially same location effect;
• performing, for each of the groups, a correction process that includes:
• performing a first correction to a first IC region in the respective group using a correction model that includes location effect, thereby modifying the initial IC design pattern to result in a first corrected IC design pattern in the first IC region;
• and
• copying the first corrected IC design pattern to other IC regions in the respective group, thereby replacing the initial IC design pattern in the other IC regions in the respective group with the first corrected IC design pattern;
• and
• taping-out the IC design layout to be accessible by at least one of:
• a mask making tool and a lithography tool.

A method comprising:

• receiving an integrated circuit (IC) design layout having a plurality of non-overlapping IC regions, each of the IC regions including an identical initial IC pattern;
• identifying a plurality of primary IC regions and a plurality of secondary IC regions based on a location effect analysis to the IC design layout, wherein each of the secondary IC regions is associated with one of the primary IC regions for having substantially same location effect there between;
• performing a correction process to the IC design layout using a correction model that includes proximity effect and location effect thereby resulting in a corrected IC design layout, wherein the correction process includes:
• for each one of the primary IC regions, applying a first correction thereto and resulting in a corrected IC pattern therein;
• and
• for each one of the secondary IC regions, replacing the initial IC pattern therein with the corrected IC pattern in one of the primary IC regions that is associated with the respective one of the secondary IC regions;
• and
• taping-out the corrected IC design layout to be accessible by at least one of:
• a mask making tool and an e-beam lithography tool.