Methods and Computer-Readable Media for Synthesizing a Multi-Corner Mesh-Based Clock Distribution Network for Multi-Voltage Domain and Clock Meshes and Integrated Circuits

A method of synthesizing a multi-corner mesh-based clock distribution network for a multi-voltage domain, the method comprising:

• (a) for each of a plurality of voltage domains, placing N×N max size buffers at an (n−1)st level of one of the voltage domains i until a maximum slew slewmax within the voltage domain i exceeds a defined slew threshold;
• (b) calculating maximum insertion delay values for all cases for each of the voltage domains;
• (c) if the maximum insertion delay values for all cases are associated with a single voltage domain j:
• (i) adding a max size buffer to all voltage domains except voltage domain j;
• and
• (ii) repeating steps (b) and (c);
• (d) reducing buffer sizes for each of the voltage domains, in order of decreasing skew, by:
• (i) downsizing all buffers in a k-th level of the voltage domain;
• (ii) if the downsizing step (i) does not improve a calculated skew across the plurality of voltage domains, (1) undoing the downsizing step (i) and (2) performing substep (i) for the k+1th level of the voltage domain;
• and
• (iii) otherwise, repeating substep (i);
• (e) recalculating maximum insertion delay values for all cases for each of the voltage domains;
• and
• (f) adding parallel buffers to a first level of the voltage domain having a highest maximum insertion delay until the calculated skew across the plurality of voltage domains no longer improves.