Method and apparatus for calculating delay timing values for an integrated circuit design

An apparatus comprising at least one signal processing module arranged to calculate at least one delay timing value for at least one setup timing stage within an integrated circuit design, the at least one signal processing module being arranged to:

• apply Negative/Positive Bias Temperature Instability, N/PBTI, compensation margins to delay values for elements within the at least one setup timing stage;
• calculate the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensated delay values;
• identify at least partially equivalent elements within parallel timing paths of the at least one setup timing stage;
• and
• apply reduced N/PBTI compensation margins to delay values of the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage.