Modifying a Virtual Processor Model for Hardware/Software Simulation
AssigneeSynopsys, Inc.
InventorsNeville A. Clark, James R. Torossian
Life of this patent
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Abstract
A method or apparatus for transforming a provided virtual processor model to a user virtual processor model. The method in on embodiment comprises transforming a virtual processor model to simulate a user target processor, by receiving a transformable virtual processor model having a transformable instruction set and a transformable pipeline, and transforming the transformable virtual processor model to a user virtual processor model designed to simulate a user target processor.
Claims5
A method to transform a virtual processor model to simulate a user target processor, the method comprising:
- receiving a transformable virtual processor model having a transformable instruction set and a transformable pipeline;
- transforming the transformable virtual processor model to a user virtual processor model designed to simulate a user target processor, the transforming comprising one or more of:
- adding a new instruction;
- modifying a definition of one or more instructions;
- and
- modifying a processor structure by one or more of:
- adding an additional pipeline associated with the user virtual processor model to the transformable virtual processor model;
- and
- modifying the transformable pipeline of the transformable virtual processor model according to the user virtual processor model;
- wherein at least one of the receiving, and transforming is performed by a processor.
A non-transitory computer-readable storage medium storing a set of instructions that when executed by one or more processors cause the one or more processors to perform operations comprising:
- receiving a transformable virtual processor model having a transformable instruction set and a transformable pipeline;
- transforming the transformable virtual processor model to a user virtual processor model designed to simulate a user target processor, the transforming comprising one or more of:
- adding a new instruction;
- modifying a definition of one or more instructions;
- and
- modifying a processor structure by one or more of:
- adding an additional pipeline associated with the user virtual processor model to the transformable virtual processor model;
- and
- modifying the transformable pipeline of the transformable virtual processor model according to the user virtual processor model;
- wherein at least one of the receiving, and transforming is performed by a processor.
A data processing system comprising:
- a memory;
- and
- a processor coupled to the memory, the processor designed to receive a transformable virtual processor model providing a timing accurate simulation of a seed processor, the transformable virtual processor model having a transformable instruction set and a transformable pipeline;
- the processor further configured to transform the transformable virtual processor model to a user virtual processor model having a behavior and timing accurate simulation of a user target processor, the transforming comprising at least one of the following:
- adding a new instruction;
- modifying a definition of one or more instructions;
- and
- modifying a processor structure by one or more of:
- adding an additional pipeline associated with the user virtual processor model to the transformable virtual processor model;
- and
- modifying the transformable pipeline of the transformable virtual processor model according to the user virtual processor model;
- wherein at least one of the receiving, and transforming is performed by a processor.
Dependencies are inferred from the claim text.