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US 2015/0309959 A1Published application
System and Method of Interfacing Co-Processors and Input/Output Devices via a Main Memory System
AssigneeDiablo Technologies Inc.
InventorsMichael L. Takefman, Maher Amer, Riccardo Badalone
Life of this patent
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Abstract
A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
Claims37
A device comprising:
- a processing unit;
- an I/O interface configured to communicate with a co-processing unit or input/output device;
- a host interface configured to communicate with a host memory controller of a host system over a memory bus;
- and
- a data de-interleaver configured to:
- determine an interleaving mapping of the host memory controller;
- and
- generate de-interleaved data from bit-interleaved data received from the host memory controller.
5 more elements
A device comprising:
- a processing unit;
- an I/O interface configured to communicate with a co-processing unit or input/output device;
- a host interface configured to communicate with a host memory controller of a host system over a memory bus;
- and
- a data descramble configured to:
- determine a scrambler sequence;
- and
- generate descrambled data by descrambling bit-interleaved data received from the host memory controller, wherein the bit-interleaved data is scrambled based on an address associated with the bit-interleaved data and the scramble sequence.
5 more elements
A device comprising:
- a processing unit;
- an I/O interface configured to communicate with a co-processing unit or input/output device;
- a host interface configured to communicate with a host memory controller of a host system over a memory bus;
- and
- a data de-interleaver configured to:
- identify information of an interleaving pattern of the host memory controller;
- determine that the interleaving pattern of the host memory controller is known;
- and
- generate de-interleaved data from bit-interleaved data received from the host memory controller based on the information of the interleaving pattern.
6 more elements
A device comprising:
- a processing unit;
- an I/O interface configured to communicate with a co-processing unit or input/output device;
- a host interface configured to communicate with a host memory controller of a host system over a memory bus;
- and
- an ECC generator configured to:
- identify information of an ECC generation pattern of the host memory controller;
- determine that the ECC generation pattern of the host memory controller is known;
- and
- generate ECC data from data received from the host memory controller based on the information of the ECC generation pattern.
6 more elements
A device comprising:
- a processing unit;
- an I/O interface configured to communicate with a co-processing unit or input/output device;
- a host interface configured to communicate with a host memory controller of a host system over a memory bus;
- and
- a data descrambler configured to:
- identify information of a scrambler sequence of the host memory controller;
- determine that the scrambler sequence of the host memory controller is known;
- and
- generate descrambled data from scrambled data received from the host memory controller based on the information of the scrambler sequence.
6 more elements
Dependencies are inferred from the claim text.