Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry

A method, comprising:

• generating a first request to load into a microprocessor a page table entry in response to a miss of a virtual address in a translation lookaside buffer of the microprocessor, the requested page table entry is included in a page table, the page table encompasses a plurality of cache lines including a first cache line that includes the requested page table entry;
• making a determination of whether a second cache line physically sequential to the first cache line is outside the page table;
• and
• selectively generating a second request to prefetch the second cache line into the microprocessor based at least on the determination.

A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

• computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising:
• first program code for specifying a translation lookaside buffer;
• second program code for specifying a first request to load into the microprocessor a page table entry in response to a miss of a virtual address in the translation lookaside buffer, the requested page table entry is included in a page table, the page table encompasses a plurality of cache lines including a first cache line that includes the requested page table entry;
• third program code for specifying hardware logic that makes a determination whether a second cache line physically sequential to the first cache line is outside the page table;
• and
• fourth program code for specifying a second request to prefetch the second cache line into the microprocessor, the second request is selectively generated based at least on the determination made by the hardware logic.