Arithmetic processing apparatus and method for controlling same

A method for controlling an arithmetic processing apparatus that includes:

• a first core group and a second core group each including a plurality of arithmetic processing sections, a first to an Nth (N is a positive integer) caches that process access requests from the plurality of arithmetic processing sections, and an intra-core-group bus through which the access requests from the plurality of arithmetic processing sections are provided to the first to Nth caches;
• and
• a first to an Nth inter-core-group buses each provided between a corresponding one of the first to Nth caches in the first core group and a corresponding one of the first to Nth caches in the second core group,
• the N being a plural number,
• the method comprising:
• individually storing, by the first to Nth caches in the first core group, data from a first to an Nth memory spaces in a memory, respectively,
• individually storing, by the first to Nth caches in the second core group, data from an N+1th to a 2Nth memory spaces in the memory, respectively,
• accessing and storing, by the first to Nth caches in the first core group, the data in the N+1th to 2Nth memory spaces in the memory, respectively, via the first to Nth inter-core-group buses, and
• accessing and storing, by the first to Nth caches in the second core group, the data in the first to Nth memory spaces in the memory, respectively, via the first to Nth inter-core-group buses.