Hybrid Non-Volatile Memory System

A method, comprising:

• operating a non-volatile memory system, the non-volatile memory system including a controller integrated circuit chip, one or more first integrated circuit chips each having one or more flash memory arrays formed of EEPROM based memory cells with a NAND-type architecture, and at least one second integrated circuit chip having a non-volatile random access memory of a type other than an EEPROM based flash memory, the operating of the volatile memory system including storage of data received from a host connected thereto in a process including:
• receiving from the host at the controller a stream of a first plurality of sectors of data having sequential logical addresses;
• caching in the non-volatile random access memory by the controller of the first plurality of sectors having sequential logical addresses as received from the host;
• forming by the controller of sectors of data cached in the non-volatile random access memory, including sectors of the first plurality of sectors having sequential logical addresses, into composite N page structures, where each of the pages includes one or more sectors and N is an integer greater than one;
• transferring the composite structures to one or more of the first integrated circuit chips;
• and
• writing the composite structures into N arrays on the first integrated circuit chips, wherein when writing the composite structures in the N arrays the N pages of each composite structure are written concurrently in parallel into a corresponding one of the N arrays,
• wherein the controller forms the composite structures so that when written into the N arrays, sectors of the first plurality of sectors having sequential logical addresses are written to have sequential physical addresses in a first of the N arrays.