Memory mirroring
AssigneeRambus Inc.
InventorsSteven WOO, David SECKER, Ravindranath KOLLIPARA
Life of this patent
Estimating the term…
Abstract
Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.
Claims20
A system comprising:
- a memory controller configured to transmit memory data to dual-inline memory modules (DIMMs) using two or more communication channels;
- a first communication channel coupled to said memory controller comprising a first bus;
- a first set of DIMMs coupled to said first bus;
- a second communication channel coupled to said memory controller, wherein the second communication channel comprises second and third buses;
- a second set of DIMMs coupled to said second bus;
- and
- a third set of DIMMs coupled to said third bus,
- wherein said memory controller is configured to enable storage of a primary copy of data within said second set of DIMMs coupled to said second bus and a secondary copy of data within said third set of DIMMs coupled to said third bus by transmitting a single copy of the data over the second communication channel.
A memory system comprising:
- a memory controller;
- a communication channel coupled to said memory controller and comprising buses;
- and
- a plurality of memory devices coupled to said communication channel and divided into one or more latency groups, wherein each latency group comprises a respective number of memory devices, wherein said communication channel is configured to deliver a data signal sent from said memory controller to said respective number of memory devices with substantially a same propagation time.
A method of storing data to memory devices, said method comprising:
- sending, with a memory controller, a single write operation to a first memory device and a second memory device via a communication channel, wherein said communication channel comprises respective chip selects for said first memory device and said second memory device;
- concurrently activating chip selects for said first memory device and said second memory device responsive to said single write operation;
- and
- concurrently sending, with said memory controller, a data element to said first memory device and said second memory device via said communication channel during said single write operation such that a primary copy of said data element is stored in said first memory device and a backup copy of said data element is stored in said second memory device.
Dependencies are inferred from the claim text.