US 2015/0309858 A1 · Imminent Read Failure Detection Based Upon Changes In Error Voltage Windows For NVM Cells

Abstract

Methods and systems are disclosed for imminent read failure detection based upon changes in error voltage windows for non-volatile memory (NVM) cells. In certain embodiments, data stored within an array of NVM cells is checked at a first time using a diagnostic mode and high/low read voltage sweeps to determine a first error voltage window where high/low uncorrectable errors are detected. Stored data is then checked at a second time using the diagnostic mode and high/low read voltage sweeps to determine a second error voltage window where high/low uncorrectable errors are detected. The difference between the error voltage windows are then compared against a voltage difference threshold value to determine whether or not to indicate an imminent read failure condition. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.

Claims20

Dependent claims

A method for detecting imminent read failures for a non-volatile memory (NVM) system, comprising:

at a first time:
performing a low read voltage sweep for an array of non-volatile memory (NVM) cells to determine a first low error voltage level;
performing a high read voltage sweep for the array of NVM cells to determine a first high error voltage level;
defining a first voltage window based upon a difference between the first high error voltage level and the first low error voltage level;
at a second time:
performing a low read voltage sweep for the array of NVM cells to determine a second low error voltage level;
performing a high read voltage sweep for the array of NVM cells to determine a second high error voltage level;
and
defining a second voltage window based upon a difference between the second high error voltage level and the second low error voltage level;
comparing a difference between the first voltage window and the second voltage window to a voltage difference threshold value;
and
indicating an imminent read failure for the array of NVM cells based upon the comparison.

9 more elements

A non-volatile memory (NVM) system having imminent read failure detection, comprising:

a non-volatile memory (NVM) including an array of NVM cells;
a memory management unit coupled to the array of NVM cells;
a controller within the memory management unit coupled to the NVM and configured to determine from a diagnostic mode run at a first time a first voltage window associated with a difference between a first low error voltage level determined from a low read voltage sweep and a first high voltage error level determined from a high read voltage sweep, to determine from the diagnostic mode run at a second time a second voltage window associated with a difference between a second low error voltage level determined from a low read voltage sweep and a second high voltage error level determined from a high read voltage sweep, to compare a difference between the first and second voltage windows to a voltage difference threshold value, and to indicate an imminent read failure for the array of NVM cells based upon the comparison.

Dependencies are inferred from the claim text.

Imminent Read Failure Detection Based Upon Changes In Error Voltage Windows For NVM Cells

Life of this patent

Imminent Read Failure Detection Based Upon Changes In Error Voltage Windows For NVM Cells

Life of this patent

Abstract

Claims20