Instruction That Performs A Scatter Write
AssigneeIntel Corporation
InventorsWEI-YU CHEN, GUEI-YUAN LUEH, SUBRAMANIAM MAIYURAN, SUPRATIM PAL
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Abstract
A processor is described having an instruction execution pipeline. The instruction execution pipeline has an instruction fetch stage to fetch an instruction specifying multiple target resultant registers. The instruction execution pipeline has an instruction decode stage to decode the instruction. The instruction execution pipeline has a functional unit to prepare resultant content specific to each of the multiple target resultant registers. The instruction execution pipeline has a write-back stage to write back said resultant content specific to each of said multiple target resultant registers.
Claims20
A processor, comprising:
- an instruction execution pipeline having:
- an instruction fetch stage to fetch an instruction specifying multiple target resultant registers;
- an instruction decode stage to decode said instruction;
- a functional unit to prepare resultant content specific to each of said multiple target resultant registers;
- and,
- a write-back stage to write back said resultant content specific to each of said multiple target resultant registers.
A computing system, comprising:
- a) a processor, said processor having an instruction execution pipeline, said instruction execution pipeline having:
- an instruction fetch stage to fetch an instruction specifying multiple target resultant registers;
- an instruction decode stage to decode said instruction;
- a functional unit to prepare resultant content specific to each of said multiple target resultant registers;
- and,
- a write-back stage to write back said resultant content specific to each of said multiple target resultant registers;
- b) a memory coupled to said processor.
A machine readable medium containing program code that when processed by a computing system causes a method to be performed, said method comprising:
- compiling a software program into program code by:
- recognizing an operation that specifies resultants targeted for multiple vectors;
- instantiating an instruction into said program code having an instruction format that specifies multiple target registers for said resultants
Dependencies are inferred from the claim text.