Computer Processor With Generation Renaming
AssigneeBroadcom Corporation
InventorsSophie WILSON, John REDFORD, Geoffrey BARRETT, Tariq KURD
Life of this patent
Estimating the term…
Abstract
A processor including a register file having a plurality of registers, and configured for out-of-order instruction execution, further includes a renamer unit that produces generation numbers that are associated with register file addresses to provide a renamed version of a register that is temporally offset from an existing version of that register rather than assigning a non-programmer-visible physical register as the renamed register. The processor includes a small reset DHL Gshare branch prediction unit coupled to an instruction cache and configured to provide speculative addresses to the instruction cache.
Claims20
A processor, comprising:
- a reservation queue;
- a renamer coupled to the reservation queue and configured to produce a generation number and to communicate the generation number to the reservation queue;
- a register coupled to the reservation queue and configured to store a value;
- an execution pipe coupled to the reservation queue;
- and
- a buffer coupled to the execution pipe and configured to receive an output of the execution pipe, and further coupled to the reservation queue and configured to communicate the output of the execution pipe to the reservation queue.
A processor comprising:
- an instruction cache;
- an instruction decoder coupled to the instruction cache;
- a reservation queue coupled to the instruction decoder;
- a register coupled to the reservation queue and configured to store a value;
- a small reset DHL Gshare branch prediction unit coupled to the instruction cache and configured to generate an address and communicate that address to the instruction cache;
- an execution pipe coupled to the reservation queue;
- a buffer coupled to the execution pipe and configured to receive an output of the execution pipe, and further coupled to the reservation queue and configured to communicate the output of the execution pipe to the reservation queue.
A processor comprising:
- an instruction cache;
- an instruction decoder coupled to the instruction cache;
- a branch prediction unit coupled to the instruction cache and configured to generate an instruction address and provide that instruction address to the instruction cache;
- a register file coupled to receive a register address;
- a renamer unit coupled to the instruction cache and to the instruction decoder;
- a plurality of reservation queues, each reservation queue of the plurality of reservation queues coupled to the register file, the instruction decoder, and the renamer unit;
- a plurality of execution pipes, each execution pipe of the plurality of execution pipes coupled to a corresponding one of the plurality of reservation queues, and configured to receive an instruction and data from the corresponding one of the plurality of reservation queues, and to execute the instruction;
- a stunt box coupled to each execution pipe of the plurality of execution pipes, and configured to receive an output of each execution pipe of the plurality of execution pipes;
- wherein, responsive to an output of the instruction decoder, the register file is configured to provide the contents of a register specified as a source in an instruction;
- and responsive to the output of the instruction decoder, the renamer is configured to concurrently provide a generation number.
Dependencies are inferred from the claim text.