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US 2015/0309793 A1Published application
Resource locking for load store scheudling in a vliw processor
AssigneeBroadcom Corporation
InventorTariq KURD
Life of this patent
Estimating the term…
Abstract
A load/store unit including a memory queue configured to store a plurality of memory instructions and state information indicating whether each memory instruction of the plurality of memory instructions can be performed independently, with, separately, or after older pending instructions; and a state-selection circuit configured to set a state information of each memory instruction of the plurality of memory instructions in view of an older pending instruction in the memory queue.
Claims39
A method comprising:
- receiving, by a load/store queue, a memory instruction requiring a first memory resource;
- comparing, by a state-selection circuit, the memory instruction against an older memory instruction stored in the load/store queue and requiring a second memory resource;
- and
- setting a status, by the state-selection circuit, to indicate whether (i) the memory instruction can be performed independent of the older memory instruction;
- (ii) the memory instruction can be performed if the older memory instruction cannot be performed;
- (iii) the memory instruction can be performed concurrently with the older memory instruction;
- or (iv) the memory instruction must be performed, if at all, after the older memory instruction is performed.
4 more elements
An apparatus comprising:
- a memory queue configured to store a plurality of memory instructions and state information indicating whether each memory instruction of the plurality of memory instructions can be performed independently, with, separately, or after older pending instructions;
- and
- a state-selection circuit configured to set a state information of each memory instruction of the plurality of memory instructions in view of an older pending instruction in the memory queue.
A method comprising:
- identifying, by a state-update circuit, a first instruction that is an oldest non-evaluated pending memory instruction;
- determining, by the state-update circuit, whether the first instruction is currently eligible to be issued;
- modifying, by the state-update circuit, a state for each remaining non-evaluated instruction whose state indicated that it could be issued when the first instruction issued to indicate that the instructions are independent if the determination is affirmative;
- and
- marking, by a load/store unit control logic circuit, the first instruction as eligible to be performed if the determination is affirmative.
2 more elements
A apparatus comprising:
- a memory queue configured to store a plurality of memory instructions and state information indicating whether each memory instruction of the plurality of memory instructions can issue independently, with, separately, or after older pending operations and if it is eligible to be performed;
- and
- a state update circuit configured to update a state information for a first instruction indicating the relation between the first instruction and an older pending instruction based on if the older pending instruction is eligible to be performed.
Dependencies are inferred from the claim text.