Reducing latency for pointer chasing loads
AssigneeApple Inc.
InventorsStephan G. Meier, Pradeep Kanapathipillai, Sandeep Gupta
Life of this patent
Estimating the term…
Abstract
Systems, methods, and apparatuses for reducing the load to load/store address latency in an out-of-order processor. When a producer load is detected in the processor pipeline, the processor predicts whether the producer load is going to hit in the store queue. If the producer load is predicted not to hit in the store queue, then a dependent load or store can be issued early. The result data of the producer load is then bypassed forward from the data cache directly to the address generation unit. This result data is then used to generate an address for the dependent load or store, reducing the latency of the dependent load or store by one clock cycle.
Claims20
A processor comprising:
- a load-store unit (LSU);
- and
- a store queue;
- wherein the processor is configured to:
- determine that a younger memory operation is dependent on an older load operation;
- issue the younger memory operation N clock cycles subsequent to the older load operation responsive to determining that the older load operation is predicted to hit in the store queue, wherein N is a positive integer;
- and
- issue the younger memory operation M clock cycles subsequent to the older load operation responsive to determining that the older load operation is predicted to miss in the store queue, wherein M is a positive integer less than N.
A method comprising:
- determining that a younger memory operation is dependent on an older load operation;
- issuing the younger memory operation N clock cycles subsequent to the older load operation responsive to determining that the older load operation is predicted to hit in a store queue, wherein N is a positive integer;
- and
- issuing the younger memory operation M clock cycles subsequent to the older load operation responsive to determining that the older load operation is predicted to miss in the store queue, wherein M is a positive integer less than N.
A system comprising:
- a processor;
- and
- a memory;
- wherein the processor is configured to:
- determine that a younger memory operation is dependent on an older load operation;
- issue the younger memory operation N clock cycles subsequent to the older load operation responsive to determining that the older load operation is predicted to hit in a store queue, wherein N is a positive integer;
- and
- issue the younger memory operation M clock cycles subsequent to the older load operation responsive to determining that the older load operation is predicted to miss in the store queue, wherein M is a positive integer less than N.
Dependencies are inferred from the claim text.