Two-stage read/write 3d architecture for memory devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuang Ting Chen, Ching-Wei Wu
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Abstract
Some embodiments of the present disclosure relate to a memory device wherein a single memory cell array is partitioned between two or more tiers which are vertically integrated on a single substrate. The memory device also includes support circuitry including a control circuit configured to read and write data to the memory cells on each tier, and a shared input/output (I/O) architecture which is connected the memory cells within each tier and configured to receive input data word prior to a write operation, and further configured to provide output data word after a read operation. Other devices and methods are also disclosed.
Claims20
A memory device comprising:
- a first memory cell array on a first tier;
- and
- a second memory cell array on a second tier, the second tier being arranged in an integrated circuit package which encloses both the first and second tiers so the second tier is arranged over the first tier, or vice versa;
- and
- a control circuit configured to perform a first read/write operation by writing a first data value to a first group of memory cells on the first tier while concurrently reading a second data value from a second group of memory cells on the second tier.
A method to read and write memory, comprising:
- partitioning a memory array into first and second tiers, wherein the second tier resides over the first tier;
- and
- performing a first read/write operation by writing a first data value to a first group of memory cells on the first tier while concurrently reading a second data value from a second group of memory cells on the second tier.
A memory device comprising:
- first and second memory cell arrays arranged in an integrated circuit package and residing on first and second tiers, respectively, wherein the second tier is arranged over the first tier, or vice versa;
- a control circuit configured to:
- perform a write operation by partitioning an N-bit input data word into first and third data values each comprising N/2-bits, writing the first data value to a first group of memory cells on the first tier in a first interval, and writing the third data value to a third group of memory cells on the second tier in a second interval;
- and
- perform a read operation by reading a second data value from a second group of memory cells on the second tier in the first interval, reading a fourth data value from a fourth group of memory cells on the first tier in the second interval, wherein the second and fourth data values each comprise N/2-bits, and assembling the second and fourth data values into a N-bit output data word;
- and
- a shared input/output (I/O) architecture which is connected the first and second tiers and configured to receive the N-bit input data word prior to the write operation and further configured to output the N-bit output data word after the read operation.
Dependencies are inferred from the claim text.