Semiconductor memory devices and memory systems including the same

A memory system comprising:

• a semiconductor memory device configured to store data, the semiconductor memory device including:
• a memory cell array including a plurality of bank arrays, each of the plurality of bank arrays including a plurality of sub-arrays;
• and
• a control logic configured to control an access to the memory cell array based on a command and an address signal, the control logic being configured to dynamically set a keep-away zone;
• and
• a memory controller configured to control the semiconductor memory device,
• wherein the keep-away zone includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled, the first word-line being coupled to a first memory cell row of a first sub-array among the plurality of sub-arrays.

A memory device comprising:

• a memory cell array including a plurality of bank arrays, each of the plurality of bank arrays including a plurality of sub-arrays;
• an address register;
• a row decoder;
• a column decoder;
• and
• a control logic configured to control an access to the memory cell array based on a command and an address signal, the control logic being configured to dynamically set a keep-away zone,
• wherein the keep-away zone includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled, the first word-line being coupled to a first memory cell row of a first sub-array among the plurality of sub-arrays, and
• wherein the control logic is configured to access the first memory cell row and a second memory cell row by partially overlapping a first row cycle for the first word-line with a second row cycle for a second word-line, the second word-line being coupled to the second memory cell row of a second sub-array among the plurality of sub-arrays, the second sub-array being in an overlappable region other than the keep-away zone.