Shared Memory Controller and Method of Using Same

A controller for a shared memory, comprising:

• a command scanner configured to concurrently scan-in a plurality of read/write commands for respective transactions and divide each of the respective transactions into respective beat-level read/write commands;
• and
• a plurality of read/write arbiters corresponding to a plurality of shared memory blocks in the shared memory, coupled to the command scanner, and configured to:
• generate respective sequences of beat-level read/write commands corresponding to the plurality of shared memory blocks with concurrent arbitration of the respective beat-level read/write commands according to respective priorities, and
• concurrently dispatch the respective sequences to the plurality of shared memory blocks to access the plurality of shared memory blocks.

A system on a chip (SOC), comprising:

• a plurality of shared memory blocks having a plurality of respective addresses;
• a plurality of processors configured to generate a plurality of respective read/write commands to access the plurality of shared memory blocks via corresponding transactions that are divisible into respective pluralities of beats;
• and
• a shared memory controller coupled between the plurality of shared memory blocks and the plurality of processors, and having:
• a command scanner configured to concurrently scan-in and divide the plurality of respective read/write commands into respective pluralities of beat-level read/write commands, and
• a plurality of read/write arbiters corresponding to the plurality of shared memory blocks and configured to:
• generate respective sequences of beat-level read/write commands corresponding to the plurality of shared memory blocks with concurrent arbitration of the respective pluralities of beat-level read/write commands for the plurality of shared memory blocks according to respective priorities, and
• concurrently dispatch the respective sequences to the plurality of shared memory blocks.