Multiple Rate Signature Test to Verify Integrated Circuit Identity
AssigneeTexas Instruments Incorporated
InventorsSoy Ying Seah, Gunvant Patel
Life of this patent
Estimating the term…
Abstract
Screening a batch of integrated circuits (IC) may be done with test patterns provided in a sequence of test vectors. The sequence of test vectors may be fetched from a memory coupled to a tester and then one or more bits from each test vector may be provided to the tester. A test pattern is formed by updating a latch in a periodic manner with a bit value from a same bit position from each of the sequence of test vectors. The test pattern may then be applied to an input pin of a device under test and a resulting signal may be monitored on an output pin of each one of the batch of ICs. A slow speed ICs may be screened by treating each IC that passes both a fast pattern test and a slow speed pattern test as a failure, for example.
Claims14
A method for screening a plurality of integrated circuits (IC), the method comprising:
- fetching a sequence of test vectors from a memory coupled to a tester;
- providing one or more bits from each test vector to the tester;
- forming a test pattern by updating a latch in a periodic manner with a bit value from a same bit position from each of the sequence of test vectors;
- and
- applying the test pattern to an input pin and monitoring a resulting signal on an output pin of each one of the plurality of ICs.
A test system comprising:
- a processor coupled to a memory circuit, the memory being loaded with instructions for execution by the processor and with a sequence of data words containing a test pattern;
- a direct memory access (DMA) engine coupled to the memory circuit;
- a latch coupled to receive data from the DMA engine;
- and
- pin circuitry coupled to the latch for coupling to a device under test (DUT);
- wherein by executing the instructions the test system performs method for screening a plurality of integrated circuits (IC), the method comprising:
- fetching a sequence of test vectors from the memory;
- providing one or more bits from each test vector to the tester;
- forming a test pattern by updating the latch in a periodic manner with a bit value from a same bit position from each of the sequence of test vectors;
- and
- applying the test pattern to an input pin and monitoring a resulting signal on an output pin of each one of the plurality of ICs.
Dependencies are inferred from the claim text.