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US 2015/0293866 A1Published application
Plc system having a plurality of cpu modules and control method thereof
AssigneeLsis Co., Ltd.
InventorsSoo Gang LEE, Dae Hyun KWON
Life of this patent
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Abstract
Disclosed is a PLC system having a plurality of CPU modules and a control method thereof, wherein the method includes ascertaining a clock signal when a count is a count corresponding to a time slot allocated by a master CPU module, generating a clock signal by accessing to a backplane, and ending generation of clock signal at a time when the access to the backplane ends.
Claims15
A PLC system comprising:
- a first CPU module configured to determine a time slot allocated for indicating a count accessible to a backplane, and to access to the backplane at the allocated time slot;
- and
- a plurality of second CPU modules respectively accessing to the backplane at the time slot allocated by the first CPU module, wherein
- the first CPU module and the plurality of the second CPU modules generate a clock signal when accessed to the backplane, and each of the first CPU module and the plurality of the second CPU modules includes a detector configured to detect a clock signal generated by the first CPU module and the plurality of the second CPU modules accessed to the backplane.
1 more element
A control method of PLC system having a plurality of CPU modules, the method comprising:
- determining a time slot allocated for indicating a count accessible to the backplane;
- ascertaining a clock signal when the count is a count corresponding to an allocated time slot;
- accessing to the backplane;
- and
- synchronizing counts at a time when the access to the backplane ends.
2 more elements
A control method of PLC system having a plurality of CPU modules, the method comprising:
- ascertaining a clock signal when a count is a count corresponding to a time slot allocated by a master CPU module of the plurality of CPU modules;
- accessing to a backplane and generating a clock signal by the plurality of CPU modules;
- and
- ending generation of clock signal at a time when the access to the backplane ends by the plurality of CPU modules.
1 more element
Dependencies are inferred from the claim text.