Buffer circuit with reduced static leakage through controlled body biasing in fdsoi technology

A circuit, comprising:

• a fully depleted silicon on insulator (FDSOI) substrate;
• a first inverter circuit fabricated on said FDSOI substrate including:
• a p-channel MOSFET having a gate terminal configured to receive a first digital signal and further having a transistor body;
• and
• an n-channel MOSFET having a gate terminal configured to receive the first digital signal and further having a transistor body connected to a source terminal of the n-channel MOSFET;
• a second inverter fabricated on said FDSOI substrate and having an input coupled to an output of the first inverter circuit and having an output configured to generate a second digital signal;
• and
• a feedback circuit configured to apply the second digital signal as a bias to the transistor body of the p-channel MOSFET of the first inverter circuit.

A circuit, comprising:

• an input line configured to receive a first digital signal having a first logic state and a second logic state referenced, respectively, to a first high voltage and a first low voltage of a first supply domain;
• a first inverter circuit including:
• a p-channel MOSFET having a gate terminal connected to the input line, a source-drain path and a transistor body;
• and
• an n-channel MOSFET having a gate terminal connected to the input line, a source-drain path coupled in series with the source-drain path of the p-channel MOSFET and a transistor body connected to a source terminal of the n-channel MOSFET;
• a second inverter having an input coupled to an output of the first inverter circuit and having an output configured to generate a second digital signal having a first logic state and a second logic state referenced, respectively, to a second high voltage and a second low voltage of a second supply domain different from the first supply domain;
• an output line connected to the output of the second inverter;
• and
• a feedback circuit configured to apply the second digital signal as a bias to the transistor body of the p-channel MOSFET of the first inverter circuit.