Butted contact shape to improve sram leakage current

A method of forming an integrated chip, comprising:

• forming a dielectric layer over a first lower level and a second lower level;
• etching a first outer region of the dielectric layer overlying the first lower level at a first etch rate to form a first outer opening extending from a top of the dielectric layer to the first lower level;
• etching a second outer region of the dielectric layer overlying the second lower level at a second etch rate to form a second outer opening extending from the top of the dielectric layer to the second lower level;
• etching a central region of the dielectric layer overlying the first lower level and the second lower level at a third etch rate, less than the first etch rate and the second etch rate, to form a central opening extending from the top of the dielectric layer to the first lower level and the second lower level;
• and
• concurrently depositing metal within the first outer opening, the second outer opening, and the central opening to form a butted contact.

A method of forming an integrated chip, comprising:

• forming a gate structure above an active area disposed within a semiconductor substrate;
• forming a lightly doped drain region within the semiconductor substrate that has a lower doping concentration than the active area, wherein the active area abuts the lightly doped drain region;
• and
• forming a butted contact, comprising a central region located above a junction of the gate structure and the lightly doped drain region, a first outer region extending from the central region to a first end of the butted contact and located entirely above the gate structure, and a second outer region extending from the central region to a second end of the butted contact, opposite the first end, and located entirely above the lightly doped drain region.