Core level optimized low power mode
AssigneeQUALCOMM Incorporated
InventorsSachin Dileep DASNURKAR, Prasad Rajeevalochanam BHADRI
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Abstract
A method for operating an electronic system, an integrated circuit on a substrate, and an apparatus including a memory and at least one processor coupled to the memory are provided. In one configuration, the at least one processor is configured to read, from an integrated circuit, first information of a first group including at least one core in a power domain and second information of a second group including at least one core in the power domain; to determine a voltage for the power domain in a low power mode based on the first information and the second information; and to configure power supply to provide the voltage for the power domain in the low power mode.
Claims20
An method for operating an electronic system, comprising:
- reading, from an integrated circuit, first information of a first group including at least one core in a power domain and second information of a second group including at least one core in the power domain;
- determining a voltage for the power domain in a low power mode based on the first information and the second information;
- and
- configuring a power supply to provide the voltage for the power domain in the low power mode.
An apparatus, comprising:
- a memory;
- and
- at least one processor coupled to the memory and configured to:
- read, from an integrated circuit, first information of a first group including at least one core in a power domain and second information including a second group of at least one core in the power domain;
- determine a voltage for the power domain in a low power mode based on the first information and the second information;
- and
- configure a power supply to provide the voltage for the power domain in the low power mode.
An integrated circuit on a substrate, comprising:
- a first core and a second core in a common power domain;
- a power supply configured to supply a voltage to the common power domain in a low power mode;
- and
- a memory storing first information of a first group including at least the first core and second information of a second group including at least the second core, wherein the voltage supplied to the common power domain in the low power mode is based on the first information or the second information.
Dependencies are inferred from the claim text.