# US 2015/0178221 A1 · Level One Data Cache Line Lock and Enhanced Snoop Protocol During Cache Victims and Writebacks to Maintain Level One Data Cache and Level Two Cache Coherence

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- Number: US 2015/0178221 A1
- Document ID: US20150178221A1
- Status: Published application
- Kind: A1
- Application number: 14/637,580
- Filed: 2015-03-04
- Published: 2015-06-25
- Earliest claimed: 2010-09-28
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Raguram Damodaran; Abhijeet Ashok Chachad; Jonathan (Son) Hung Tran; David Matthew Thompson
- Web page: https://patentgrep.com/patent/US20150178221A1

## CPC

- G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA]
- G06F 1/3296: by lowering the supply or operating voltage
- G06F 7/483: Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)}
- G06F 9/3012: {Organisation of register space, e.g. banked or distributed register file}
- G06F 11/1064: {in cache or content addressable memories}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/12: Replacement control
- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 13/18: based on priority control (G06F13/1605 takes precedence)
- H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply}
- H03K 21/00: Details of pulse counters or frequency dividers
- H03M 13/2903: {Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes}
- H03M 13/353: {Adaptation to the channel}
- G06F 13/1652: {in a multiprocessor architecture (interprocessor communication using common memory G06F15/167)}
- G06F 13/1657: {Access to multiple memories}
- G06F 13/1663: {Access to shared memory}
- G06F 13/364: using independent requests or grants, e.g. using separated request and grant lines
- G06F 2212/1021: Hit rate improvement
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/221: Static RAM
- G06F 2212/2532: comprising a plurality of modules
- G06F 2212/283: Plural cache memories
- G06F 2212/608: Details relating to cache mapping
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer to be retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write.

## Claims

### Claim at position 1

1-2. (canceled)

### Claim 3

In a data processing system including a central processing unit executing program instructions to manipulate data, a first level data cache temporarily storing in a plurality of first cache lines data for manipulation by the central processing unit, a second level memory including second level cache temporarily storing in a plurality of second cache lines data for manipulation by the central processing unit and a second level local memory directly addressable by the central processing unit and a direct memory access unit operating under control of the central processing unit to control data transfers including transferring data into and out of the second level local memory, a method of data processing operation comprising the steps of:
initiating a victim entry in a first victim buffer upon selection of a first cache line in the first level data cache for replacement,
storing a first victim address corresponding to data stored in a first cache line selected for replacement and data stored in said first cache line selected for replacement in the victim entry of the first victim buffer;
receiving snoop write data and a corresponding snoop write address;
comparing the first victim address of each entry in the first victim buffer to the snoop write address;
writing the snoop write data into a corresponding entry in said first victim buffer upon a match between a snoop write address and a first victim address in said first victim buffer;
retiring a victim entry of the first victim buffer upon committing said first cache line selected for replacement to the second level memory;
initiating a victim entry in a second victim buffer upon selection of a first cache line in the first level data cache for replacement;
storing a second victim address corresponding to data stored in said first cache line selected for replacement and the data stored in the first cache line selected for replacement in a victim entry in the second victim buffer;
receiving direct memory access write data and a corresponding direct memory access write address of a direct memory access unit controlled data transfer;
comparing the second victim address of each entry in said second victim buffer to the direct memory access write address;
writing the direct memory access write data into a corresponding entry in said second victim buffer upon a match between a direct memory access write address and a second victim address in said second victim buffer and forwarding a snoop write to the first level cache if there is no match between the direct memory access write address and the second victim address in said second victim buffer; and
retiring a victim entry of the second victim buffer upon committing said first cache line selected for replacement to the second level memory.

### Claim 4 (depends on 3)

The method of data processing of claim 3, wherein:
storing a tag indicating a valid and a dirty status of the data stored in each cache line of the first level cache;
storing a set of shadow tags corresponding to the tags of the first level data cache in the second level memory;
comparing the shadow tags and the direct memory access write address; and
forwarding a snoop write to the first level cache a shadow tag address matches a direct memory access write address.