# US 2015/0178084 A1 · Instruction and logic for processing text strings

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- Number: US 2015/0178084 A1
- Document ID: US20150178084A1
- Status: Published application
- Kind: A1
- Application number: 14/562,641
- Filed: 2014-12-05
- Published: 2015-06-25
- Earliest claimed: 2006-09-22
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Michael A. Julier; Jeffrey D. Gray; Srinivas Chennupaty; Sean P. Mirkes; Mark P. Seconi
- Web page: https://patentgrep.com/patent/US20150178084A1

## CPC

- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 7/06: Arrangements for sorting, selecting, merging, or comparing data on individual record carriers
- G06F 9/30: Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22)
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30021: {Compare instructions, e.g. Greater-Than, Equal-To, MINMAX}
- G06F 9/30029: {Logical and Boolean instructions, e.g. XOR, NOT}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/30098: {Register arrangements}
- G06F 9/30109: {having multiple operands in a single register}
- G06F 9/3013: {according to data content, e.g. floating-point registers, address registers}
- G06F 9/30167: {of immediate specifier, e.g. constants}
- G06F 9/3017: {Runtime instruction translation, e.g. macros}
- G06F 9/30185: {according to one or more bits in the instruction, e.g. prefix, sub-opcode}
- G06F 9/30192: {according to data descriptor, e.g. dynamic data typing}
- G06F 9/3802: {Instruction prefetching}
- G06F 9/3853: {of compound instructions}
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 9/34: Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)}
- G06F 9/3824: {Operand accessing}
- G06F 9/3885: {using a plurality of independent parallel functional units}
- G06F 2212/452: Instruction code
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

## Claims

### Claim 1

A hand held device comprising:
a plurality of system components, including:
a liquid crystal display controller;
a dynamic random access memory;
a direct memory access controller;
a wireless transceiver;
a network controller;
a flash memory device;
a graphics controller;
a memory controller; and
an audio controller; and
a processor coupled to the plurality of system components, the processor comprising:
a first logic to fetch a compare instruction;
a decoder logic to decode the compare instruction;
a plurality of 64-bit single-instruction multiple data (SIMD) floating point data registers, including:
a first and second 64-bit SIMD floating point data register to store a first and second 64-bit SIMD floating point operand, respectively, wherein each of the first and second 64-bit SIMD floating point operands comprise two 32-bit SIMD floating point data elements;
a 64-bit SIMD destination register, into which at least one result of performing the compare instruction is to be stored, wherein the first and second 64 bit floating point data operands and the 64-bit SIMD destination register are to be identified by a first and second SIMD operand field and a SIMD destination field, respectively, within the compare instruction;
a plurality of execution units, wherein at least one execution unit of the plurality of execution units is to execute the compare instruction, wherein the compare instruction is to cause the processor to:
determine whether each of the 32-bit SIMD floating point data elements of the first and second SIMD floating point operands is valid,
compare only valid 32-bit SIMD floating point data elements of the first 32-bit SIMD floating point operand with only valid 32-bit SIMD floating point data elements of the second 32-bit SIMD floating point operand, wherein the valid 32-bit SIMD floating point data elements of the first 32-bit SIMD floating point operand to be compared with the valid 32-bit SIMD floating point data elements of the second 32-SIMD floating point operand are in in the same data element position, and
store a plurality of indicators of whether the compared valid 32-bit SIMD floating point data elements of the first 32-bit SIMD floating point operand and the valid 32-bit SIMD floating point data elements of the second 32-bit SIMD floating point operand are equal.

### Claim 2 (depends on 1)

The hand held device of claim 1, wherein the graphics controller and the memory controller are integrated on the same die as the processor.

### Claim 3 (depends on 1)

The hand held device of claim 1, wherein the field to indicate one of a plurality of data element sizes is a 2-bit field.

### Claim 4 (depends on 1)

The hand held device of claim 1, wherein the compare instruction is a first compare instruction, the first logic to fetch a second compare instruction to compare a first plurality of packed integer data elements with a second plurality of packed integer data elements, wherein at least one execution unit of the plurality of execution units is to execute the second compare instruction, wherein the second compare instruction is to cause the processor to:
compare integer data elements of the first plurality of packed integer data elements with integer data elements of the second plurality of packed integer data elements, and
store a plurality of expanded data elements, each of a first multi-bit size, to indicate whether the compared integer data elements of the first plurality of packed integer data elements and the integer data elements of the second plurality of packed integer data elements are equal.

### Claim 5 (depends on 1)

The hand held device of claim 1, wherein the processor is a RISC processor.

### Claim 6 (depends on 1)

The hand held device of claim 1, wherein the hand held device is a cellular phone.

### Claim 7 (depends on 1)

The hand held device of claim 1, wherein the wireless transceiver is a Bluetooth wireless transceiver.

### Claim 8 (depends on 1)

The hand held device of claim 1, wherein the plurality of system components further include a Universal Serial Bus port.