# US 2015/0177458 A1 · Bonding of heterogeneous material grown on silicon to a silicon photonic circuit

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- Number: US 2015/0177458 A1
- Document ID: US20150177458A1
- Status: Published application
- Kind: A1
- Application number: 14/577,938
- Filed: 2014-12-19
- Published: 2015-06-25
- Earliest claimed: 2013-12-20
- Assignees: The Regents of the University of California
- Applicants: The Regents of the University of California
- Inventors: John E. BOWERS; Jock BOVINGTON
- Web page: https://patentgrep.com/patent/US20150177458A1

## CPC

- G02B 6/12002: {Three-dimensional structures}
- G02B 6/131: {by using epitaxial growth (epitaxial growth for semiconductors H10P14/20)}
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS

## Abstract

A method of fabricating a heterogeneous semiconductor wafer includes depositing a III-V type semiconductor epitaxial layer on a first wafer having a semiconductor substrate. The first wafer is then bonded to a second wafer having a patterned silicon layer formed on a semiconductor substrate, wherein the III-V type semiconductor epitaxial layer is bonded to the patterned silicon layer of the second wafer. The semiconductor substrate associated with the first wafer is removed to expose the III-V type semiconductor epitaxial layer.

## Claims

### Claim 1

A method of fabricating a heterogeneous semiconductor wafer, the method comprising:
depositing a III-V type semiconductor epitaxial layer on a first wafer having a semiconductor substrate;
bonding the first wafer to a second wafer having a patterned silicon layer formed on a semiconductor substrate, wherein the III-V type semiconductor epitaxial layer is bonded to the patterned silicon layer of the second wafer; and
removing the semiconductor substrate associated with the first wafer to expose the III-V type semiconductor epitaxial layer.

### Claim 2 (depends on 1)

The method of claim 1, further including:
depositing a buffer layer on the semiconductor substrate associated with the first wafer, wherein the III-V type semiconductor epitaxial layer is deposited on the buffer layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the buffer layer comprises one or more of Germanium (Ge), Silicon Germanium (SiGe), Strontium Titanate (SrTO3), and Silicon Dioxide (SiO2).

### Claim 4 (depends on 1)

The method of claim 1, wherein the III-V type semiconductor epitaxial layer comprises one or more of quantum dots, quantum wells, quantum wires, quantum dashes.

### Claim 5 (depends on 1)

The method of claim 1, further including:
processing the exposed III-V type semiconductor epitaxial layer following removal of the semiconductor substrate to form one or more active optoelectronic devices coupled to the patterned silicon layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the one or more active optoelectronic devices includes one or more laser, photodetector, modulator, phase tuning element, interferometric device, wavelength multiplexer, polarization splitter, coupler, or saturable absorber.

### Claim 7 (depends on 5)

The method of claim 5, wherein the patterned silicon layer includes one or more passive optical components coupled to the one or more active optoelectronic devices formed within the III-V type semiconductor epitaxial layer.

### Claim 8 (depends on 7)

The method of claim 7, wherein the passive optical components include one or more of waveguides, filters, and/or splitters.

### Claim 9 (depends on 1)

The method of claim 1, wherein the second wafer is a silicon-on-insulator wafer that includes a silicon substrate, a buried oxide layer deposited on the silicon substrate, and the patterned silicon layer formed on the buried oxide layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein bonding the first wafer to the second wafer includes providing electrical conductivity between the patterned silicon layer and the III-V type semiconductor epitaxial layer.

### Claim 11 (depends on 1)

The method of claim 1, wherein the second wafer includes a metal layer that includes a thin contact metal stack on top of the patterned silicon layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein bonding includes annealing under pressure to form covalent bonds between the patterned silicon layer and the III-V type semiconductor epitaxial layer and interdiffusion between the thin contact metal stack and the III-V type semiconductor epitaxial layer.

### Claim 13 (depends on 1)

The method of claim 1, wherein the bonding process is selected from the group consisting of: hydrophilic bonding, hydrophobic bonding, plasma assisted bonding, solder bonding, metal bonding, and polymer bonding (e.g., benzocyclobutene bonding).

### Claim 14 (depends on 1)

The method of claim 1, wherein the semiconductor substrates associated with the first and second wafers, respectively, are silicon substrates.

### Claim 15

A heterogeneous wafer comprising:
a first wafer having a semiconductor substrate and a patterned silicon layer; and
a second wafer having a semiconductor substrate and a III-V type semiconductor epitaxial layer;
wherein the second wafer is bonded to the first wafer such that the III-V type semiconductor epitaxial layer is bonded to the patterned silicon layer.

### Claim 16 (depends on 15)

The heterogeneous wafer of claim 15, wherein a diameter of the first wafer is approximately equal to a diameter of the second wafer.

### Claim 17 (depends on 16)

The heterogeneous wafer of claim 16, wherein the diameter of the first wafer and the second wafer is greater than 200 millimeters (mm).

### Claim 18 (depends on 16)

The heterogeneous wafer of claim 16, wherein the second wafer includes a buffer layer deposited on the semiconductor substrate, herein the III-V type semiconductor epitaxial layer is deposited on the buffer layer.

### Claim 19 (depends on 18)

The heterogeneous wafer of claim 18, wherein the buffer layer comprises one or more of Germanium (Ge), Silicon Germanium (SiGe), Strontium Titanate (SrTO3), and Silicon Dioxide (SiO2) and the III-V type semiconductor layer comprises one or more of quantum dots, quantum wells, quantum wires, quantum dashes.

### Claim 20 (depends on 15)

The heterogeneous wafer of claim 15, wherein the III-V type semiconductor epitaxial layer is processed to form one or more active optoelectronic devices coupled to the patterned silicon layer.

### Claim 21 (depends on 20)

The heterogeneous wafer of claim 20, wherein the one or more active optoelectronic devices includes one or more laser, photodetector, modulator, phase tuning element, interferometric device, wavelength multiplexer, polarization splitter, coupler, or saturable absorber and wherein the patterned silicon layer includes one or more passive optical components coupled to the one or more active optoelectronic devices formed within the III-V type epitaxial layer.

### Claim 22 (depends on 15)

The heterogeneous wafer of claim 15, wherein the first wafer is a silicon-on-insulator wafer that includes a silicon substrate, a buried oxide layer deposited on the silicon substrate, and the patterned silicon layer formed on the buried oxide layer.

### Claim 23 (depends on 15)

The heterogeneous wafer of claim 15, wherein bonding between the first wafer and the second wafer includes creation of electrical conductivity between the patterned silicon layer and the III-V type semiconductor epitaxial layer.

### Claim 24 (depends on 23)

The heterogeneous wafer of claim 23, wherein the first wafer includes a metal layer having a thin contact metal stack located on top of the patterned silicon layer that is bonded via interdiffusion with the III-V type semiconductor epitaxial layer.

### Claim 25 (depends on 15)

The heterogeneous wafer of claim 15, wherein the semiconductor substrates associated with the first and second wafers, respectively, are silicon substrates.