# US 2015/0149685 A1 · Pci-e standard selection setting system and microserver > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0149685 A1 - Document ID: US20150149685A1 - Status: Published application - Kind: A1 - Application number: 14/256,109 - Filed: 2014-04-18 - Published: 2015-05-28 - Earliest claimed: 2013-11-28 - Assignees: Inventec (Pudong) Technology Corporation; Inventec Corporation - Applicants: Inventec (Pudong) Technology Corporation; Inventec Corporation - Inventors: Lan-Lan FANG - Web page: https://patentgrep.com/patent/US20150149685A1 ## CPC - G06F 13/4068: {Electrical coupling} - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/4063: {Device-to-bus coupling} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A peripheral component interface-express (PCI-E) standard selection setting system and microserver are disclosed, in which a selection controller selects an arrangement setting in storage elements to arrange the PCI-E control chip, whereby each of the second PCI-E standard ports is or is not arranged as an upstream PCI-E standard port, so that a single PCI-E standard control chip may arrange one of the multitude of PCI-E standard ports as an upstream PCI-E standard port, so that the upstream PCI-E standard port may have a data transmission with one of the multitude of system on chips (SOCs) connected with the PCI-E standard control chip. ## Claims ### Claim 1 A microserver, comprising: a system on chip (SOC), each having a first peripheral component interface-express (PCI-E) port; a PCI-E control chip, having a plurality of second PCI-E ports each electrically connected to the first PCI-E port corresponding thereto, and generating a first selection signal; a storage element, each electrically connected to the PCI-E control chip, and having an arrangement setting stored therein; and a selection controller, receiving the first selection signal to generate a plurality of second selection signals, wherein the each of the plurality of second selection signals corresponds to a corresponding one of the storage element to control the arrangement setting stored in the storage element to arrange the PCI-E control chip, the arrangement setting selecting to arrange only one of the plurality of second PCI-E ports as an upstream PCI-E port and the upstream PCI-E port being electrically connected to the first PCI-E port for data transmission therebetween. ### Claim 2 (depends on 1) The microserver as claimed in claim 1, wherein the storage element controls the arrangement setting to select the upstream PCI-E port by using a chip select (CS) signal and the corresponding one of the plurality of second selection signals, and the storage element is electrically connected to the PCI-E control chip to transmit the selected arrangement setting to the PCI-E control chip for the arrangement. ### Claim 3 (depends on 1) The microserver as claimed in claim 1, wherein only one of the plurality of second selection signals is at a valid state. ### Claim 4 (depends on 1) The microserver as claimed in claim 1, wherein the selection controller further comprises a plurality of jumpers and a plurality of logic gates each corresponding to a corresponding one of the plurality of jumpers. ### Claim 5 (depends on 4) The microserver as claimed in claim 4, wherein each of the plurality of jumpers is composed of a first pin and a second pin, the first pin being connected to a power source to generate a third selection signal, the second pin being connected to ground, and each of the plurality of logic gates receives and has an OR logic operation on the first selection signal and the third selection signal corresponding thereto, to generate the second selection signal, respectively. ### Claim 6 (depends on 5) The microserver as claimed in claim 5, wherein one of the plurality of pins connects the first pin and the second pin through a jumper cap and is thus selected, the third selection signal generated by the first pin is at a valid state and has an OR logic operation with one of the plurality of logic gates corresponding to the selected one of the plurality of jumpers when the first selection signal is at a valid state, to generate the second selection signal at a valid state being logic low. ### Claim 7 (depends on 1) The microserver as claimed in claim 1, wherein the PCI-E control chip further comprises a universal serial bus (USB), a serial advanced technology attachment (SATA) and accelerated graphics port (AGP), and a management port at a always-on state. ### Claim 8 A microserver, comprising: a system on chip (SOC), each having a first peripheral component interface-express (PCI-E) port; a PCI-E control chip, having a plurality of second PCI-E ports each electrically connected to the first PCI-E port corresponding thereto, and generating a first selection signal; a storage element, each electrically connected to the PCI-E control chip and having an arrangement setting stored therein; and a selection controller, each electrically connected to each of the SOC to receives the first selection signal and a control signal generated by each of the SOC to generate the plurality of second selection signals each corresponding to one of the SOC, wherein the each of the plurality of second selection signals corresponds to a corresponding one of the storage element to control the arrangement setting stored in the storage element to arrange the PCI-E control chip, the arrangement setting selecting to arrange only one of the plurality of second PCI-E ports as an upstream PCI-E port and the upstream PCI-E port being electrically connected to the first PCI-E port for data transmission therebetween. ### Claim 9 (depends on 8) The microserver as claimed in claim 8, wherein the selection controller is a complex programmable logic device (CPLD) or a field programmable gate array (FPGA). ### Claim 10 A peripheral component interface-express (PCI-E) selection setting system, comprising: a PCI-E control chip, generating a first selection signal; a storage element, each electrically connected to the PCI-E control chip and having an arrangement setting stored therein; and a selection controller, each receiving the first selection signal to generate the plurality of second selection signals each corresponding to one of the storage element to control the arrangement setting in the storage element to arrange the PCI-E control chip. ### Claim 11 (depends on 10) The PCI-E selection setting system as claimed in claim 10, wherein the storage element controls the arrangement setting to select the upstream PCI-E port by using a chip select (CS) signal and the corresponding one of the plurality of second selection signals, and the storage element is electrically connected to the PCI-E control chip to transmit the selected arrangement setting to the PCI-E control chip for the arrangement. ### Claim 12 (depends on 10) The PCI-E selection setting system as claimed in claim 10, wherein only one of the plurality of second selection signals is at a valid state. ### Claim 13 (depends on 10) The PCI-E selection setting system as claimed in claim 10, wherein the selection controller further comprises a plurality of jumpers and a plurality of logic gates each corresponding to a corresponding one of the plurality of jumpers. ### Claim 14 (depends on 13) The PCI-E selection setting system as claimed in claim 13, wherein each of the plurality of jumpers is composed of a first pin and a second pin, the first pin being connected to a power source to generate a third selection signal, the second pin being connected to ground, and each of the plurality of logic gates receives and has an OR logic operation on the first selection signal and the third selection signal corresponding thereto, to generate the second selection signal, respectively. ### Claim 15 (depends on 14) The PCI-E selection setting system as claimed in claim 14, wherein one of the plurality of pins connects the first pin and the second pin through a jumper cap and is thus selected, the third selection signal generated by the first pin is at a valid state and has an OR logic operation with one of the plurality of logic gates corresponding to the selected one of the plurality of jumpers when the first selection signal is at a valid state, to generate the second selection signal at a valid state being logic low.