# US 2015/0149518 A1 · High speed and low power circuit structure for barrel shifter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0149518 A1 - Document ID: US20150149518A1 - Status: Published application - Kind: A1 - Application number: 14/611,223 - Filed: 2015-01-31 - Published: 2015-05-28 - Earliest claimed: 2012-06-29 - Assignees: International Business Machines Corporation - Inventors: Takeo Yasuda - Web page: https://patentgrep.com/patent/US20150149518A1 ## CPC - G06F 5/015: {having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. This encoding scheme allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for an implementation adapted to shift a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption. ## Claims ### Claim at position 1 -6. (canceled) ### Claim 7 A circuit for encoding selection signals to control selectors of a multi-stage barrel shifter, comprising: a sign magnitude to 2's complement converter having a sign input which receives an input shift direction for a shift operation and having a magnitude input which receives an input shift amount for the shift operation, wherein said sign magnitude to 2's complement converter uses a 2's complement of the input shift amount to generate a first decoder signal for controlling a first selector and to generate a second decoder signal for controlling a second selector. ### Claim 8 (depends on 7) The circuit of claim 7 wherein said sign magnitude to 2's complement converter computes an output result as the 2's complement of the input shift amount using the shift direction as a sign input, assigns a first portion of the output result to the first decoder signal, and assigns a second portion of the output result to the second decoder signal. ### Claim 9 (depends on 8) The circuit of claim 8 adapted for a 64-bit barrel shifter wherein: the input shift amount has 6 bits; the output result has 6 bits; the first decoder signal has 3 bits; and the second decoder signal has 3 bits. ### Claim 10 (depends on 9) The circuit of claim 9 wherein said sign magnitude to 2's complement converter generates the first and second decoder signals using no more than three stages of gates. ### Claim 11 (depends on 7) The circuit of claim 7 wherein the input shift direction has a logical high value to indicate a shift direction to the right, and has a logical low value to indicate a shift direction to the left. ### Claim 12 A barrel shifter comprising: a sign magnitude to 2's complement converter circuit having a sign input which receives an input shift direction for a shift operation and having a magnitude input which receives an input shift amount for the shift operation, wherein said sign magnitude to 2's complement converter circuit generates a first decoder signal and a second decoder signal; a first decoder circuit which derives a first selection signal from the first decoder signal; a second decoder circuit which derives a second selection signal from the second decoder signal; a first selector controlled by the first selection signal which selects an intermediate shifted value from a first plurality of shifted values representing an operand value shifted by different integer multiples of a first shift level unit amount; and a second selector controlled by the second selection signal which selects a raw shifted value from a second plurality of shifted values representing the intermediate shifted value shifted by different integer multiples of a second shift level unit amount. ### Claim 13 (depends on 12) The barrel shifter of claim 12 wherein said sign magnitude to 2's complement converter circuit computes an output result as a 2's complement of the input shift amount using the shift direction as a sign input, assigns a first portion of the output result to the first decoder signal, and assigns a second portion of the output result to the second decoder signal. ### Claim 14 (depends on 12) The barrel shifter of claim 12 wherein said sign magnitude to 2's complement converter circuit has no more than three stages of gates. ### Claim 15 (depends on 12) The barrel shifter of claim 12 wherein said first decoder circuit and said second decoder circuit have identical constructions. ### Claim 16 (depends on 12) The barrel shifter of claim 12 wherein the input shift direction has a logical high value to indicate a shift direction to the right, and has a logical low value to indicate a shift direction to the left. ### Claim 17 (canceled) ### Claim 18 (depends on 12) The barrel shifter of claim 12 wherein said first and second selectors use transfer gate multiplexers. ### Claim 19 (depends on 12) The barrel shifter of claim 12, further comprising an output multiplexer for converting the raw shifted data into final shifted data. ### Claim 20 In a barrel shifter which shifts an operand value in a single clock cycle using cascaded multiplexer selectors, the improvement comprising: a sign magnitude to 2's complement converter circuit having a sign input which receives an input shift direction for a shift operation and having a magnitude input which receives an input shift amount for the shift operation, said sign magnitude to 2's complement converter circuit generating decoder signals for controlling the cascaded multiplexer selectors. ### Claim 21 (depends on 20) The improvement of claim 20 wherein said sign magnitude to 2's complement converter circuit computes an output result as a 2's complement of the input shift amount using the shift direction as a sign input, assigns a first portion of the output result to a first decoder signal, and assigns a second portion of the output result to a second decoder signal. ### Claim 22 (depends on 20) The improvement of claim 20 wherein the barrel shifter is adapted to shift a 64-bit operand value and said sign magnitude to 2's complement converter circuit generates the decoder signals using no more than three stages of gates. ### Claim at position 18 -25. (canceled)