# US 2015/0146830 A1 · Clock recovery for a data receiving unit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0146830 A1 - Document ID: US20150146830A1 - Status: Published application - Kind: A1 - Application number: 14/548,087 - Filed: 2014-11-19 - Published: 2015-05-28 - Earliest claimed: 2013-11-28 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Peter Buchmann; Pier Andrea Francese; Thomas H. Toifl - Web page: https://patentgrep.com/patent/US20150146830A1 ## CPC - H03L 7/00: Automatic control of frequency or phase; Synchronisation - H04L 7/0025: {interpolation of clock signal} - H04L 7/0337: {Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Clock recovery for a data receiving unit is disclosed. Clock recovery can include obtaining an early/late signal from an incoming data stream, wherein the early/late signal indicates if a set of one or more data samples of the incoming data stream tends to be earlier or later than an edge of a phase-rotated clock signal provided depending on a phase offset value. Clock recovery can include updating a phase rotation counter value in response to the early/late signal. Clock recovery can include determining the phase offset value depending on a rounded phase rotation counter value. The phase offset value can be further determined by selecting one of a set of options including maintaining, increasing, or decreasing the rounded phase rotation counter value, wherein the selecting is performed depending on the early/late signal and depending on the phase rotation counter value. ## Claims ### Claim 1 A method of clock recovery for a data receiving unit, comprising: obtaining an early/late signal from an incoming data stream, wherein the early/late signal indicates if a set of one or more data samples of the incoming data stream tends to be earlier or later than an edge of a phase-rotated clock signal provided depending on a phase offset value; updating a phase rotation counter value in response to the early/late signal; and determining the phase offset value depending on a rounded phase rotation counter value; wherein the phase offset value is further determined by selecting one of a set of options including maintaining, increasing, and decreasing the rounded phase rotation counter value, wherein the selecting is performed depending on the early/late signal and depending on the phase rotation counter value. ### Claim 2 (depends on 1) The method according to claim 1, wherein the updating of the phase rotation counter value in response to the early/late signal is performed by applying a proportional value to the phase rotation counter value depending on the early/late signal and, by applying an integrator value to the phase rotation counter value, wherein the integrator value is obtained by integrating a provided integrator value depending on the early/late signal. ### Claim 3 (depends on 1) The method according to claim 1, wherein the early/late signal is obtained by applying a majority voting method on a number of data samples of the incoming data stream. ### Claim 4 (depends on 1) The method according to claim 1, wherein the phase offset value corresponds to the rounded phase rotation counter value, wherein the selecting of one of the set of options including maintaining, increasing, or decreasing the rounded phase rotation counter value is performed depending on the early/late signal and depending on a rounding error of the rounded phase rotation counter value. ### Claim 5 (depends on 4) The method according to claim 4, wherein the rounded phase rotation counter value corresponds to a value of a number of most significant bits of the phase rotation counter value, wherein the phase offset value corresponds to the value of the most significant bits of the phase rotation counter value which is maintained, incremented or decremented depending on the early/late signal and depending on a value of a number of least significant bits of the phase rotation counter value. ### Claim 6 (depends on 5) The method according to claim 5, wherein the value of the most significant bits of the phase rotation counter value is incremented to obtain the phase offset value if the early/late signal indicates that the set of one or more data samples of the incoming data stream tends to be later than an edge of the phase-rotated clock signal and the value of the least significant bits of the phase rotation counter value is within a predetermined range. ### Claim 7 (depends on 6) The method according to claim 6, wherein the value of the most significant bits of the phase rotation counter value is decremented to obtain the phase offset value if the early/late signal indicates that the set of one or more data samples of the incoming data stream tends to be earlier than an edge of the phase-rotated clock signal and the value of the least significant bits of the phase rotation counter value is within a predetermined range. ### Claim 8 (depends on 1) The method according to claim 1, wherein a first time for updating the phase rotation counter value in response to the early/late signal and determining the phase offset value depending on a rounded phase rotation counter value is longer than a second time for selecting one of the set of options including maintaining, increasing, or decreasing the rounded phase rotation counter value, wherein the selecting is performed depending on the early/late signal and depending on the phase rotation counter value. ### Claim 9 (depends on 8) The method according to claim 8, wherein the rounded phase rotation counter value is incremented depending on whether a rounding error of the rounding of the phase rotation counter value is within a predetermined range and the early/late signal indicates that the set of one or more data samples of the incoming data stream tends to be later than an edge of the phase-rotated clock signal. ### Claim 10 (depends on 9) The method according to claim 9, wherein the rounded phase rotation counter value is decremented depending on whether the rounding error of the rounding of the phase rotation counter value is within a further predetermined range and the early/late signal indicates that the set of one or more data samples of the incoming data stream tends to be later than an edge of the phase-rotated clock signal. ### Claim 11 (depends on 8) The method according to claim 8, wherein a number of consecutive early/late signals are considered, wherein the rounded phase rotation counter value is incremented if a rounding error of the rounding of the phase rotation counter value is within a range which is determined by the number of early/late signals each indicating that the set of one or more data samples of the incoming data stream tends to be later than an edge of the phase-rotated clock signal. ### Claim 12 (depends on 11) The method according to claim 11, wherein the rounded phase rotation counter value is decremented if the rounding error of the rounding of the phase rotation counter value is within a range which is determined by the number of early/late signals each indicating that the set of one or more data samples of the incoming data stream tends to be earlier than an edge of the phase-rotated clock signal. ### Claim 13 A clock recovery apparatus for a data receiving unit, comprising: an early/late aggregation block configured to obtain an early/late signal from an incoming data stream, wherein the early/late signal indicates whether a set of one or more data samples of the incoming data stream tends to be earlier or later than an edge of a phase-rotated clock signal provided depending on a phase offset value, and a phase rotation counter block configured to update a phase rotation counter value in response to the early/late signal, configured to determine the phase rotation counter value, and configured to determine the phase offset value depending on a rounded phase rotation counter value; and a look-ahead unit configured to determine the phase offset value by selecting one of the set of options including maintaining, increasing or decreasing the rounded phase rotation counter value wherein the selecting is performed depending on the early/late signal and depending on the phase rotation counter value. ### Claim 14 (depends on 13) The clock recovery apparatus according to claim 13, wherein the phase rotation counter block is configured to apply a proportional value to the phase rotation counter value depending on the early/late signal and, apply an integrator value to the phase rotation counter value, wherein the integrator value is obtained by an integrator block which is configured to integrate a provided integrator value depending on the early/late signal. ### Claim 15 (depends on 13) The clock recovery apparatus according to claim 13, wherein the early/late aggregation block is configured to obtain the early/late signal by applying a majority voting method on a number of data samples of the incoming data stream. ### Claim 16 (depends on 13) The clock recovery apparatus according to claim 13, wherein the phase offset value corresponds to the rounded phase rotation counter value, wherein the look-ahead unit is further configured to select one of the set of options depending on the early/late signal and depending on a rounding error of the rounded phase rotation counter value. ### Claim 17 (depends on 16) The clock recovery apparatus according to claim 16, wherein the rounded phase rotation counter value corresponds to a value of a number of most significant bits of the phase rotation counter value, wherein the phase offset value corresponds to the value of the most significant bits of the phase rotation counter value which is maintained, incremented or decremented depending on the early/late signal and depending on a value of a number of least significant bits of the phase rotation counter value. ### Claim 18 (depends on 17) The clock recovery apparatus according to claim 17, wherein the look-ahead unit is further configured to increment the value of the most significant bits of the phase rotation counter value to obtain the phase offset value if the early/late signal indicates that the set of one or more data samples of the incoming data stream tends to be later than an edge of the phase-rotated clock signal and the value of the least significant bits of the phase rotation counter value is within a predetermined range. ### Claim 19 (depends on 18) The clock recovery apparatus according to claim 18, wherein the look-ahead unit is further configured to decrement the value of the most significant bits of the phase rotation counter value to obtain the phase offset value if the early/late signal indicates that the set of one or more data samples of the incoming data stream tends to be earlier than an edge of the phase-rotated clock signal and the value of the least significant bits of the phase rotation counter value is within a predetermined range. ### Claim 20 A method of clock recovery for a data receiving unit, comprising: receiving an early/late signal from an incoming data stream, wherein the early/late signal indicates whether a set of one or more data samples of the incoming data stream is earlier than or later than an edge of a phase-rotated clock signal, the phase-rotated clock signal provided depending on a phase offset value; updating a phase rotation counter value in response to receiving the early/late signal; determining a rounded phase rotation counter value depending on the phase rotation counter value and the early/late signal; and determining the phase offset value depending on the rounded phase rotation counter value.