# US 2015/0146818 A1 · Reader receivers and reader transceivers including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0146818 A1 - Document ID: US20150146818A1 - Status: Published application - Kind: A1 - Application number: 14/546,311 - Filed: 2014-11-18 - Published: 2015-05-28 - Earliest claimed: 2013-11-25 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jun-Ho Kim; Il-Jong Song; Hang-Seok Choi - Web page: https://patentgrep.com/patent/US20150146818A1 ## CPC - H04L 27/00: Modulated-carrier systems - H04L 27/0014: {Carrier regulation (of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657)} - H04B 5/266: {One coil at each side, e.g. with primary and secondary coils} - H04L 2027/0036: {using a recovered symbol clock} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H04B: TRANSMISSION ## Abstract Reader receivers including a sample clock providing unit are provided. The sample clock providing unit may be configured to generate a plurality of first clock signals of equivalent frequency that are out-of-phase relative to each other and further configured to generate first and second sample clock signals of unequal phase from selected ones of the plurality of first clock signals by comparing a respective phase of each of the plurality of first clock signals against a phase of a reference clock signal. ## Claims ### Claim 1 A reader receiver, comprising: a sample clock providing circuit configured to generate a plurality of delayed clock signals by controlling a phase of an initial clock signal, configured to select one of the plurality of delayed clock signals as a sample clock signal based on an input signal and further configured to provide an I phase sample clock signal and a Q phase sample clock signal based on the sample clock signal; a mixer configured to convert the input signal into base band signals in synchronization with the I phase sample clock signal and the Q phase sample clock signal, respectively; and a base band signal processing circuit configured to filter and amplify the base band signals. ### Claim 2 (depends on 1) The reader receiver of claim 1, wherein the sample clock providing circuit includes: a reference clock generator configured to generate a reference clock signal based on the input signal; an initial clock generator configured to generate the initial clock signal; a clock delay circuit configured to generate the plurality of delayed clock signals by delaying the initial clock signal; a phase comparator configured to provide a selection signal by comparing a respective phase of each of the plurality of delayed clock signals against a phase of the reference clock signal; and a selector configured to output the I phase sample clock signal and the Q phase sample clock signal by selecting the one of the plurality of delayed clock signals as the sample clock signal based on the selection signal. ### Claim 3 (depends on 2) The reader receiver of claim 2, wherein the clock delay circuit includes a plurality of delay cells configured to provide the plurality of delayed clock signals by controlling the phase of the initial clock signal, and wherein an interval of controlling a phase of the sample clock signal decreases as a number of the plurality of delayed clock signals increases. ### Claim 4 (depends on 3) The reader receiver of claim 3, wherein the one of the plurality of delayed clock signals selected as the sample clock signal is most closely aligned in phase to the reference clock signal. ### Claim 5 (depends on 3) The reader receiver of claim 3, wherein the sample clock providing circuit is configured to control the phase of the sample clock signal to reduce a phase noise of the sample clock signal. ### Claim 6 (depends on 2) The reader receiver of claim 2, wherein the phase comparator includes: a phase comparing circuit configured to output phase difference signals by comparing the respective phase of each of the plurality of delayed clock signals against the phase of the reference clock signal; and a ranking generator configured to determine phase difference rankings of the phase difference signals and configured to provide the selection signal based on the phase difference rankings. ### Claim 7 (depends on 6) The reader receiver of claim 6, wherein phase differences between the reference clock signal and each of the plurality of delayed clock signals are represented as pulse widths corresponding to the respective phase differences. ### Claim 8 (depends on 7) The reader receiver of claim 7, wherein the phase comparing circuit is configured to output the phase difference signals by converting the pulse widths to amplitudes of voltages or currents. ### Claim 9 (depends on 8) The reader receiver of claim 8, wherein each of the phase difference rankings is digital code provided based on the amplitudes of the voltages or the currents. ### Claim 10 (depends on 9) The reader receiver of the claim 9, wherein the ranking generator is configured to arrange the digital codes in a descending order or an ascending order. ### Claim 11 (depends on 10) The reader receiver of the claim 10, wherein values of the phase difference signals decrease as values of the digital codes increase when the digital codes are arranged in the descending order, and a first digital code of the arranged digital codes is provided as the selection signal. ### Claim 12 (depends on 10) The reader receiver of the claim 10, wherein values of the phase difference signals increase as values of the digital codes increase when the digital codes are arranged in the ascending order, and a last digital code of the arranged digital codes is provided as the selection signal. ### Claim 13 A reader transceiver comprising: a reader transmitter configured to transmit an output signal in synchronization with a transmission clock signal; and a reader receiver configured to process an input signal, wherein the reader receiver includes: a sample clock providing circuit configured to generate a plurality of delayed clock signals by controlling a phase of an initial clock signal, configured to select one of the plurality of delayed clock signals as a sample clock signal based on an input signal and further configured to provide an I phase sample clock signal and a Q phase sample clock signal based on the sample clock signal; a mixer configured to convert the input signal into base band signals in synchronization with the I phase sample clock signal and the Q phase sample clock signal, respectively; and a base band signal processing circuit configured to filter and amplify the base band signals. ### Claim 14 (depends on 13) The reader transceiver of claim 13, wherein the I phase sample clock signal and the Q phase sample clock signal are provided by controlling a phase of the transmission clock signal. ### Claim 15 (depends on 13) The reader transceiver of claim 13, further comprising a phase trace circuit configured to perform a tracing process for the I phase sample clock signal and the Q phase sample clock signal between an end of a reader transmission interval and a start of a reader reception interval. ### Claim 16 A near field communication (NFC) receiver, comprising: a sample clock generator configured to generate a plurality of first clock signals of equivalent frequency that are out-of-phase relative to each other and further configured to generate first and second sample clock signals of unequal phase from selected ones of the plurality of first clock signals by comparing a respective phase of each of the plurality of first clock signals against a phase of a reference clock signal recovered from an input signal; and a mixer configured to convert the input signal into a pair of base band signals that are synchronized with the first and second sample clock signals. ### Claim 17 (depends on 16) The NFC receiver of claim 16, further comprising a base band signal processor configured to filter and amplify the pair of base band signals. ### Claim 18 (depends on 16) The NFC receiver of claim 16, wherein said comparing a respective phase of each of the plurality of first clock signals against a phase of a reference clock signal comprises identifying which of the plurality of first clock signals is most closely aligned in phase to the reference clock signal. ### Claim 19 (depends on 18) The NFC receiver of claim 18, wherein said identifying which of the plurality of first clock signals is most closely aligned in phase to the reference clock signal comprises passing the plurality of first clock signals in sequence through a phase comparing circuit and a phase ranking generator. ### Claim 20 (depends on 19) The NFC receiver of claim 19, wherein the phase comparing circuit utilizes a plurality of XNOR gates at a front end thereof to determine degrees of phase alignment between the reference clock signal and each of the plurality of first clock signals.