# US 2015/0146491 A1 · In-memory computational device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0146491 A1 - Document ID: US20150146491A1 - Status: Published application - Kind: A1 - Application number: 14/555,638 - Filed: 2014-11-27 - Published: 2015-05-28 - Earliest claimed: 2013-11-28 - Assignees: Gsi Technology Israel Ltd. - Applicants: Mikamonu Group Ltd. - Inventors: Avidan AKERIB; Eli EHRMAN - Web page: https://patentgrep.com/patent/US20150146491A1 ## CPC - G11C 15/04: using semiconductor elements - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G11C 7/18: Bit line organisation; Bit line lay-out - G11C 8/10: Decoders - G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A computing device comprising includes a memory array having a plurality of sections with memory cells arranged in rows and column, at least one cell in each column of the memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0. The computing device additionally includes at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from the first section and a decoder to activate a word line connected to a cell in the column in the second section to write the bit line voltage into the cell. ## Claims ### Claim 1 A computing device comprising: a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0; and at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from said first section; and a decoder to activate a word line connected to a cell in said column in said second section to write said bit line voltage into said cell. ### Claim 2 (depends on 1) A computing device according to claim 1 further comprising a controller to provide said decoder with an instruction set for decoding in said decoder. ### Claim 3 (depends on 2) A computing device according to claim 2 wherein said instruction set is of a small size. ### Claim 4 (depends on 3) A computing device according to claim 3 wherein said instruction set from said controller comprises a maximum size of 64 bits. ### Claim 5 (depends on 2) A computing device according to claim 2 wherein said instruction set represents compressed data associated with the operation of any one of said memory array, said at least one multiplexer, and said decoder. ### Claim 6 (depends on 5) A computing device according to claim 5 wherein said decoder decompresses said compressed data. ### Claim 7 (depends on 1) A computing device according to claim 1 wherein said decoder activates said at least one multiplexer to connect said bit lines in said first section and said second section. ### Claim 8 (depends on 1) A computing device according to claim 1 wherein said decoder simultaneously accesses a plurality of read word lines and write word lines in said memory array. ### Claim 9 (depends on 2) A computing device according to claim 2 wherein said decoder decodes said instruction set from said controller into an instruction set for accessing in parallel a plurality of read word lines and write word lines in said memory array. ### Claim 10 (depends on 1) A computing device according to claim 1 wherein said decoder comprises a memory array comprising a plurality memory cells arranged in rows and column, at least one cell in each column connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0. ### Claim 11 (depends on 10) A computing device according to claim 10 wherein activation of said word line is through said bit line in said decoder. ### Claim 12 (depends on 1) A computing device according to claim 1 wherein said at least one cell connected to a bit line comprises only one memory cell in each column. ### Claim 13 (depends on 1) A computing device according to claim 1 wherein said at least one cell connected to a bit line comprises all the memory cells in each column. ### Claim 14 (depends on 1) A computing device according to claim 1 wherein said memory cells comprise non-destructive cells. ### Claim 15 (depends on 1) A computing device according to claim 1 wherein said memory cells comprise volatile memory cells. ### Claim 16 A method of performing in-memory computations in a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0, the method comprising: connecting a bit line in a column of a first section to a bit line in a column in a second section different from said first section; and activating a word line connected to a cell in said column in said second section; and writing said bit line voltage into said cell. ### Claim 17 (depends on 16) A method according to claim 16 further comprising decompressing compressed data represented by a small size instruction set into a large size instruction set. ### Claim 18 (depends on 16) A method according to claim 16 further comprising simultaneously accessing a plurality of read word lines and write word lines. ### Claim 19 (depends on 16) A method according to claim 16 further comprising decoding an instruction set from a controller into an instruction set comprising a plurality of read and write commands. ### Claim 20 (depends on 16) A method according to claim 16 further comprising activating said word line with a bit line voltage.