# US 2015/0146485 A1 · Method of programming non-volatile memory device and non-volatile memory device using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0146485 A1 - Document ID: US20150146485A1 - Status: Published application - Kind: A1 - Application number: 14/614,992 - Filed: 2015-02-05 - Published: 2015-05-28 - Earliest claimed: 2008-10-21 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Moosung KIM; Ohsuk KWON - Web page: https://patentgrep.com/patent/US20150146485A1 ## CPC - G11C 16/12: Programming voltage switching circuits - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 16/24: Bit-line control circuits - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 16/3454: {Arrangements for verifying correct programming or for detecting overprogrammed cells} - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7206: Reconfiguration of flash memory system - G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising} - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 2211/5621: Multilevel programming verification - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A program method of a nonvolatile memory device according to example embodiments includes a operation (a) of detecting a level of a program voltage; and a operation (b) of providing a unselected word line voltage and a bit line precharge voltage having a variable level respectively according to the detected level of the program voltage. ## Claims ### Claim at position 1 -18. (canceled) ### Claim 19 A method of operating a nonvolatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including multi-level memory cells coupled to word lines and bit lines, the method comprising: performing a first program operation on selected memory cells coupled to a selected word line using a first incremental Step Pulse Program (ISPP) scheme, the first program operation including, applying a first pass voltage to an unselected word line during a first program period; applying a second pass voltage higher than the first pass voltage to the unselected word line during a second program period following the first program period; and applying a third pass voltage higher than the second pass voltage to the unselected word line during a third program period following the second program period, wherein the first program period includes at least two program loops, each of the second program period and the third program period includes at least one program loop, and memory cells coupled to the unselected word line and the selected memory cells coupled to the selected word line are included in a same memory block among the plurality of memory blocks. ### Claim 20 (depends on 19) The method of claim 19, wherein the first program operation is a most significant bit (MSB) page program operation. ### Claim 21 (depends on 19) The method of claim 19, further comprising: performing a second program operation on the selected memory cells coupled to the selected word line using a second ISPP scheme, wherein the second program operation is a least significant bit (LSB) page program operation. ### Claim 22 (depends on 21) The method of claim 21, wherein the second program operation is followed by the first program operation. ### Claim 23 (depends on 21) The method of claim 21, wherein the performing a second program operation includes applying a fourth pass voltage to the unselected word line during a fourth program period. ### Claim 24 (depends on 23) The method of claim 23, wherein the fourth pass voltage is equal to the first pass voltage. ### Claim 25 (depends on 23) The method of claim 23, wherein the fourth pass voltage is different from the first pass voltage. ### Claim 26 A method of operating a nonvolatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including multi-level memory cells coupled to word lines and bit lines, the method comprising: applying a program voltage to a selected word line coupled to first memory cells and second memory cells among the multi-level memory cells; applying a first pass voltage to an unselected word line until programming the first memory cells into a first target state is completed; and applying a second pass Voltage higher than the first pass voltage to the unselected word line after the programming the first memory cells into the first target state is completed, wherein memory cells coupled to the unselected word line and the first memory cells are included in a same selected memory block among the plurality of memory blocks. ### Claim 27 (depends on 26) The method of claim 26, further comprising: applying the second pass voltage to the unselected word line until programming the second memory cells into a second target state is completed; and applying a third pass voltage higher than the second pass voltage to the unselected word line after the programming the second memory cells into the second target state is completed. ### Claim 28 A method of operating a nonvolatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including multi-level memory cells coupled to word lines and bit lines, the method comprising: performing a least significant bit (LSB) page program operation on selected memory cells coupled to a selected word line using a first Incremental Step Pulse Program (ISPP) scheme, the LSB page program operation including applying a first pass voltage to an unselected word line; performing a most significant bit (MSB) page program operation on the selected memory cells coupled to the selected word line using a second ISPP scheme, the MSB page program operation including, applying a second pass voltage higher than the first pass voltage to the unselected word line during a first program loop; applying a third pass voltage higher than the second pass voltage to the unselected word line during a second program loop following the first program loop; and applying a fourth pass voltage higher than the third pass voltage to the unselected word line during a third program loop following the second program loop, wherein memory cells coupled to the unselected word line and the selected memory cells are included in a same selected memory block among the plurality of memory blocks.